^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * and RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001, 2003-2005 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/txx9/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/txx9/tx4927.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int __init tx4927_report_pciclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int pciclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pr_info("PCIC --%s PCICLK:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) " PCI66" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) switch ((unsigned long)ccfg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TX4927_CCFG_PCIDIVMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case TX4927_CCFG_PCIDIVMODE_2_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pciclk = txx9_cpu_clock * 2 / 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case TX4927_CCFG_PCIDIVMODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pciclk = txx9_cpu_clock / 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case TX4927_CCFG_PCIDIVMODE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pciclk = txx9_cpu_clock / 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case TX4927_CCFG_PCIDIVMODE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pciclk = txx9_cpu_clock / 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pr_cont("Internal(%u.%uMHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (pciclk + 50000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ((pciclk + 50000) / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pr_cont("External");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pciclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int __init tx4927_pciclk66_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Assert M66EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tx4927_ccfg_set(TX4927_CCFG_PCI66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Double PCICLK (if possible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int pcidivmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pcidivmode = (unsigned long)ccfg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TX4927_CCFG_PCIDIVMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) switch (pcidivmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case TX4927_CCFG_PCIDIVMODE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case TX4927_CCFG_PCIDIVMODE_2_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pciclk = txx9_cpu_clock * 2 / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case TX4927_CCFG_PCIDIVMODE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case TX4927_CCFG_PCIDIVMODE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pciclk = txx9_cpu_clock / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pcidivmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_debug("PCICLK: ccfg:%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pciclk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __init tx4927_setup_pcierr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tx4927_pcierr_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0, "PCI error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (void *)TX4927_PCIC_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_warn("Failed to request irq for PCIERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags
| Donate