^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001,2002,2003 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * BCM1250-specific PCI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This module provides the glue between Linux's PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and the hardware. We basically provide glue for accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * configuration space, and set up the translation for I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * space accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * To access configuration space, we use ioremap. In the 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * kernel, this consumes either 4 or 8 page table pages, and 16MB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * kernel mapped memory. Hopefully neither of these should be a huge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/vt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/sibyte/sb1250_defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/sibyte/board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Macros for calculating offsets into config space given a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * structure or dev/fun/reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void *cfg_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_BUS_ENABLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LDT_BUS_ENABLED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_MODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int sb1250_bus_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_BRIDGE_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LDT_BRIDGE_DEVICE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_SIBYTE_HAS_LDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * HT's level-sensitive interrupts require EOI, which is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * through a 4MB memory-mapped region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long ldt_eoi_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Read/write 32-bit values in config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline u32 READCFG32(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return *(u32 *) (cfg_space + (addr & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline void WRITECFG32(u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *(u32 *) (cfg_space + (addr & ~3)) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Some checks before doing config cycles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * In PCI Device Mode, hide everything on bus 0 except the LDT host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * bridge. Otherwise, access is controlled by bridge MasterEn bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) devno = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (devno == LDT_BRIDGE_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else if (sb1250_bus_status & PCI_DEVICE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Read/write access functions for various sizes of values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * in config space. Return all 1's for disallowed accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * for a kludgy but adequate simulation of master aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (sb1250_pci_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) data = READCFG32(CFGADDR(bus, devfn, where));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) data = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cfgaddr = CFGADDR(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!sb1250_pci_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) data = READCFG32(cfgaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) WRITECFG32(cfgaddr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pci_ops sb1250_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .read = sb1250_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .write = sb1250_pcibios_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct resource sb1250_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "SB1250 PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .start = 0x40000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .end = 0x5fffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct resource sb1250_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "SB1250 PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .start = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .end = 0x01ffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pci_controller sb1250_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pci_ops = &sb1250_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mem_resource = &sb1250_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .io_resource = &sb1250_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int __init sb1250_pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void __iomem *io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) uint32_t cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) uint64_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* CFE will assign PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Avoid ISA compat ranges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PCIBIOS_MIN_IO = 0x00008000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PCIBIOS_MIN_MEM = 0x01000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Set I/O resource limits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iomem_resource.end = 0xffffffffUL; /* no HT support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cfg_space =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * See if the PCI bus has been configured by the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!(reg & M_SYS_PCI_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sb1250_bus_status |= PCI_DEVICE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cmdreg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) READCFG32(CFGOFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PCI_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!(cmdreg & PCI_COMMAND_MASTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ("PCI: Skipping PCI probe. Bus is not initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) iounmap(cfg_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sb1250_bus_status |= PCI_BUS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * space. Use "match bytes" policy to make everything look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * little-endian. So, you need to also set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * CONFIG_SWAP_IO_SPACE, but this is the combination that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * works correctly with most of Linux's drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * XXX ehs: Should this happen in PCI Device mode?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sb1250_controller.io_map_base = (unsigned long)io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) set_io_port_base((unsigned long)io_map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifdef CONFIG_SIBYTE_HAS_LDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Also check the LDT bridge's enable, just in case we didn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * initialize that one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PCI_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (cmdreg & PCI_COMMAND_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sb1250_bus_status |= LDT_BUS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Need bits 23:16 to convey vector number. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * this consumes 4MB of kernel-mapped memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * (Kseg2/Kseg3) for 32-bit kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ldt_eoi_space = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 4 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) register_pci_controller(&sb1250_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_VGA_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) console_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) arch_initcall(sb1250_pcibios_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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