^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ralink RT3662/RT3883 SoC PCI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Parts of this file are based on Ralink's 2.6.21 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach-ralink/rt3883.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RT3883_MEMORY_BASE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RT3883_MEMORY_SIZE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RT3883_PCI_REG_PCICFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RT3883_PCICFG_PCIRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RT3883_PCI_REG_PCIRAW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RT3883_PCI_REG_PCIINT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RT3883_PCI_REG_PCIENA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RT3883_PCI_REG_CFGADDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RT3883_PCI_REG_CFGDATA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RT3883_PCI_REG_MEMBASE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RT3883_PCI_REG_IOBASE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RT3883_PCI_REG_ARBCTL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RT3883_PCI_MODE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RT3883_PCI_MODE_PCI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RT3883_PCI_MODE_PCIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RT3883_PCI_IRQ_COUNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RT3883_P2P_BR_DEVNUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct rt3883_pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct device_node *intc_of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pci_controller pci_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct resource io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct resource mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool pcie_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct rt3883_pci_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_bus_to_rt3883_controller(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) hose = (struct pci_controller *) bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return container_of(hose, struct rt3883_pci_controller, pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ioread32(rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iowrite32(val, rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int func, unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned bus, unsigned slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned func, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned bus, unsigned slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned func, unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void rt3883_pci_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) rpc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned irq, bit = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq = irq_find_mapping(rpc->irq_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pending &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void rt3883_pci_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rpc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void rt3883_pci_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rpc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct irq_chip rt3883_pci_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "RT3883 PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .irq_mask = rt3883_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .irq_unmask = rt3883_pci_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .irq_mask_ack = rt3883_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irq_set_chip_data(irq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .map = rt3883_pci_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int rt3883_pci_irq_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct rt3883_pci_controller *rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rpc->irq_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &rt3883_pci_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!rpc->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "unable to add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rpc = pci_bus_to_rt3883_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!rpc->pcie_ready && bus->number == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PCI_FUNC(devfn), where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rpc = pci_bus_to_rt3883_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!rpc->pcie_ready && bus->number == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PCI_FUNC(devfn), where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct pci_ops rt3883_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .read = rt3883_pci_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .write = rt3883_pci_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 syscfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 rstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 clkcfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (mode & RT3883_PCI_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rstctrl |= RT3883_RSTCTRL_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* setup PCI PAD drive mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) syscfg1 &= ~(0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) syscfg1 |= (2 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) t &= ~BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) t &= 0x80ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) t |= 0xa << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) t |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rstctrl &= ~RT3883_RSTCTRL_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (mode & RT3883_PCI_MODE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rstctrl &= ~RT3883_RSTCTRL_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (mode & RT3883_PCI_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rstctrl &= ~RT3883_RSTCTRL_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * setup the device number of the P2P bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * and de-assert the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (mode & RT3883_PCI_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rpc->pcie_ready = t & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!rpc->pcie_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* reset the PCIe block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) t |= RT3883_RSTCTRL_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) t &= ~RT3883_RSTCTRL_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* turn off PCIe clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) t &= ~0xf000c080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* enable PCI arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int rt3883_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct rt3883_pci_controller *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rpc->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (IS_ERR(rpc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return PTR_ERR(rpc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* find the interrupt controller child node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (of_get_property(child, "interrupt-controller", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rpc->intc_of_node = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!rpc->intc_of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(dev, "%pOF has no %s child node",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rpc->intc_of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "interrupt controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* find the PCI host bridge child node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (of_node_is_type(child, "pci")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rpc->pci_controller.of_node = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!rpc->pci_controller.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(dev, "%pOF has no %s child node",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rpc->intc_of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "PCI host bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto err_put_intc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mode = RT3883_PCI_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!of_node_is_type(child, "pci"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) devfn = of_pci_get_devfn(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (devfn < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) switch (PCI_SLOT(devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mode |= RT3883_PCI_MODE_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case 17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mode |= RT3883_PCI_MODE_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (mode == RT3883_PCI_MODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev, "unable to determine PCI mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto err_put_hb_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_info(dev, "mode:%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rt3883_pci_preinit(rpc, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rpc->pci_controller.pci_ops = &rt3883_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) rpc->pci_controller.io_resource = &rpc->io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rpc->pci_controller.mem_resource = &rpc->mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Load PCI I/O and memory resources from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pci_load_of_ranges(&rpc->pci_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rpc->pci_controller.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ioport_resource.start = rpc->io_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ioport_resource.end = rpc->io_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = rt3883_pci_irq_init(dev, rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto err_put_hb_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (mode == RT3883_PCI_MODE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PCI_BASE_ADDRESS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RT3883_MEMORY_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PCI_IO_BASE, 0x00000101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) register_pci_controller(&rpc->pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) err_put_hb_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) of_node_put(rpc->pci_controller.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) err_put_intc_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) of_node_put(rpc->intc_of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return of_irq_parse_and_map_pci(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct of_device_id rt3883_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { .compatible = "ralink,rt3883-pci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct platform_driver rt3883_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .probe = rt3883_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .name = "rt3883-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .of_match_table = of_match_ptr(rt3883_pci_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int __init rt3883_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return platform_driver_register(&rt3883_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) postcore_initcall(rt3883_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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