^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005-2009 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/swiotlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/octeon/cvmx-npi-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/octeon/cvmx-pci-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/octeon/pci-octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USE_OCTEON_INTERNAL_ARBITER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * addresses. Use PCI endian swapping 1 so no address swapping is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * necessary. The Linux io routines will endian swap the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u64 octeon_bar1_pci_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This is the bit decoding used for the Octeon PCI controller addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) union octeon_pci_address {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint64_t u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) uint64_t upper:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint64_t reserved:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint64_t io:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) uint64_t did:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) uint64_t subdid:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) uint64_t reserved2:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint64_t endian_swap:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) uint64_t reserved3:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint64_t bus:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) uint64_t dev:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint64_t func:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint64_t reg:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Map a PCI device to the appropriate interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @dev: The Linux PCI device structure for the device to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @slot: The slot number for this device on __BUS 0__. Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * enumerates through all the bridges and figures out the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * slot on Bus 0 where this device eventually hooks to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @pin: The PCI interrupt pin read from the device, then swizzled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * as it goes through each bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Returns Interrupt number for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (octeon_pcibios_map_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return octeon_pcibios_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) panic("octeon_pcibios_map_irq not set.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Called to perform platform specific PCI setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uint16_t config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uint32_t dconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Force the Cache line setting to 64 bytes. The standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Linux bus scan doesn't seem to set it. Octeon really has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 128 byte lines, but Intel bridges get really upset if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * try and set values above 64 bytes. Value is specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 32bit words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Set latency timers for all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Enable reporting System errors and parity errors on all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Enable parity checking and error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_read_config_word(dev, PCI_COMMAND, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pci_write_config_word(dev, PCI_COMMAND, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (dev->subordinate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Set latency timers on sub bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* More bridge error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Enable the PCIe normal error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Find the Advanced Error Reporting capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Clear Uncorrectable Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Enable reporting of all uncorrectable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Uncorrectable Error Mask - turned on bits disable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Leave severity at HW default. This only controls if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * errors are reported as uncorrectable or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * correctable, not if the error is reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Clear Correctable Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Enable reporting of all correctable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Correctable Error Mask - turned on bits disable errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Advanced Error Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* ECRC Generation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (config & PCI_ERR_CAP_ECRC_GENC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) config |= PCI_ERR_CAP_ECRC_GENE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* ECRC Check Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (config & PCI_ERR_CAP_ECRC_CHKC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) config |= PCI_ERR_CAP_ECRC_CHKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Report all errors to the root complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PCI_ERR_ROOT_CMD_COR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PCI_ERR_ROOT_CMD_NONFATAL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PCI_ERR_ROOT_CMD_FATAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Clear the Root status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Return the mapping of PCI device number to IRQ line. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * character in the return string represents the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * line for the device at that position. Device 1 maps to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * first character, etc. The characters A-D are used for PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Returns PCI interrupt mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const char *octeon_get_pci_interrupts(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Returning an empty string causes the interrupts to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * routed based on the PCI specification. From the PCI spec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * INTA# of Device Number 0 is connected to IRQW on the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * board. (Device Number has no significance regarding being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * located on the system board or in a connector.) INTA# of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Device Number 1 is connected to IRQX on the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * board. INTA# of Device Number 2 is connected to IRQY on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * system board. INTA# of Device Number 3 is connected to IRQZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * on the system board. The table below describes how each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * agent's INTx# lines are connected to the system board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * interrupt lines. The following equation can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * determine to which INTx# signal on the system board a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * device's INTx# line(s) is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * INTD# = 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (of_machine_is_compatible("dlink,dsr-500n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) switch (octeon_bootinfo->board_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case CVMX_BOARD_TYPE_NAO38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* This is really the NAC38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case CVMX_BOARD_TYPE_EBH3100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case CVMX_BOARD_TYPE_BBGW_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return "AABCD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case CVMX_BOARD_TYPE_CUST_DSR1000N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case CVMX_BOARD_TYPE_THUNDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case CVMX_BOARD_TYPE_EBH3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Map a PCI device to the appropriate interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @dev: The Linux PCI device structure for the device to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @slot: The slot number for this device on __BUS 0__. Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * enumerates through all the bridges and figures out the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * slot on Bus 0 where this device eventually hooks to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @pin: The PCI interrupt pin read from the device, then swizzled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * as it goes through each bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Returns Interrupt number for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int irq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const char *interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Get the board specific interrupt mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) interrupts = octeon_get_pci_interrupts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_num = dev->devfn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (dev_num < strlen(interrupts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) OCTEON_IRQ_PCI_INT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return irq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Read a value from configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int reg, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) union octeon_pci_address pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pci_addr.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pci_addr.s.upper = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pci_addr.s.io = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pci_addr.s.did = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pci_addr.s.subdid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pci_addr.s.endian_swap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_addr.s.bus = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pci_addr.s.dev = devfn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci_addr.s.func = devfn & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pci_addr.s.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *val = cvmx_read64_uint8(pci_addr.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Write a value to PCI configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int reg, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) union octeon_pci_address pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pci_addr.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_addr.s.upper = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_addr.s.io = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pci_addr.s.did = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_addr.s.subdid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pci_addr.s.endian_swap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pci_addr.s.bus = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pci_addr.s.dev = devfn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pci_addr.s.func = devfn & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pci_addr.s.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cvmx_write64_uint8(pci_addr.u64, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct pci_ops octeon_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .read = octeon_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .write = octeon_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct resource octeon_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "Octeon PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct resource octeon_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .start = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .end = OCTEON_PCI_IOSPACE_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "Octeon PCI IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct pci_controller octeon_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .pci_ops = &octeon_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .mem_resource = &octeon_pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .io_resource = &octeon_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .io_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .io_map_base = OCTEON_PCI_IOSPACE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Low level initialize the Octeon PCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void octeon_pci_initialize(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) union cvmx_pci_cfg01 cfg01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) union cvmx_npi_ctl_status ctl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) union cvmx_pci_ctl_status_2 ctl_status_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) union cvmx_pci_cfg19 cfg19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) union cvmx_pci_cfg16 cfg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) union cvmx_pci_cfg22 cfg22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) union cvmx_pci_cfg56 cfg56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Reset the PCI Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cvmx_read_csr(CVMX_CIU_SOFT_PRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) udelay(2000); /* Hold PCI reset for 2 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctl_status.s.max_word = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ctl_status.s.timer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Deassert PCI reset and advertize PCX Host Mode Device Capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (64b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cvmx_read_csr(CVMX_CIU_SOFT_PRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) udelay(2000); /* Wait 2 ms after deasserting PCI reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctl_status_2.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) before any PCI reads. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctl_status_2.s.bar2_enb = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ctl_status_2.s.bar2_esx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* BAR1 hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ctl_status_2.s.bb1 = 1; /* BAR1 is big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ctl_status_2.s.bb0 = 1; /* BAR0 is big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) udelay(2000); /* Wait 2 ms before doing PCI reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pr_notice("PCI Status: %s %s-bit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ctl_status_2.s.ap_64ad ? "64" : "32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) union cvmx_pci_cnt_reg cnt_reg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) union cvmx_pci_cnt_reg cnt_reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long cycles, pci_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cycles = read_c0_cvmcount();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cycles = read_c0_cvmcount() - cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (cycles / (mips_hpt_frequency / 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_notice("PCI Clock: %lu MHz\n", pci_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * in PCI-X mode to allow four outstanding splits. Otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * should not change from its reset value. Don't write PCI_CFG19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * in PCI mode (0x82000001 reset value), write it to 0x82000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * MRBCM -> must be one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ctl_status_2.s.ap_pcix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cfg19.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Target Delayed/Split request outstanding maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * count. [1..31] and 0=32. NOTE: If the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * programs these bits beyond the Designed Maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * outstanding count, then the designed maximum table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * depth will be used instead. No additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Deferred/Split transactions will be accepted if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * this outstanding maximum count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * reached. Furthermore, no additional deferred/split
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * transactions will be accepted if the I/O delay/ I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Split Request outstanding maximum is reached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cfg19.s.tdomc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Master Deferred Read Request Outstanding Max Count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * 5 2 110 6 3 111 7 3 For example, if these bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * programmed to 100, the core can support 2 DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * cycles, 4 SAC cycles or a combination of 1 DAC and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * 2 SAC cycles. NOTE: For the PCI-X maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * outstanding split transactions, refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * CRE0[22:20].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cfg19.s.mdrrmc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Master Request (Memory Read) Byte Count/Byte Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * select. 0 = Byte Enables valid. In PCI mode, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * burst transaction cannot be performed using Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Read command=4?h6. 1 = DWORD Byte Count valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * (default). In PCI Mode, the memory read byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * enables are automatically generated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * core. Note: N3 Master Request transaction sizes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * always determined through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * am_attr[<35:32>|<7:0>] field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cfg19.s.mrbcm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cfg01.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cfg01.s.msae = 1; /* Memory Space Access Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cfg01.s.me = 1; /* Master Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cfg01.s.pee = 1; /* PERR# Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cfg01.s.see = 1; /* System Error Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #ifdef USE_OCTEON_INTERNAL_ARBITER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * When OCTEON is a PCI host, most systems will use OCTEON's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * internal arbiter, so must enable it before any PCI/PCI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * traffic can occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_int_arb_cfg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif /* USE_OCTEON_INTERNAL_ARBITER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * 1..7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cfg16.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cfg16.s.mltd = 1; /* Master Latency Timer Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Should be written to 0x4ff00. MTTV -> must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * FLUSH -> must be 1. MRV -> should be 0xFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cfg22.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Master Retry Value [1..255] and 0=infinite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cfg22.s.mrv = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * N3K operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cfg22.s.flush = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * MOST Indicates the maximum number of outstanding splits (in -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * notation) when OCTEON is in PCI-X mode. PCI-X performance is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * affected by the MOST selection. Should generally be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * depending on the desired MOST of 3, 2, 1, or 0, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cfg56.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cfg56.s.roe = 1; /* Relaxed Ordering Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [0=512B,1=1024B,2=2048B,3=4096B] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .. 7=32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Affects PCI performance when OCTEON services reads to its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * these values need to be changed so they won't possibly prefetch off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * of the end of memory if PCI is DMAing a buffer at the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * memory. Note that these values differ from their reset values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Initialize the Octeon PCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int __init octeon_pci_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) union cvmx_npi_mem_access_subidx mem_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Only these chips have PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (octeon_has_feature(OCTEON_FEATURE_PCIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!octeon_is_pci_host()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pr_notice("Not in host mode, PCI Controller not initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Point pcibios_map_irq() to the PCI version of it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Only use the big bars on chips that support it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* PCI I/O and PCI MEM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ioport_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pr_notice("%s Octeon big bar support\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (octeon_dma_bar_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) octeon_pci_initialize();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mem_access.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mem_access.s.esr = 1; /* Endian-Swap on read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mem_access.s.esw = 1; /* Endian-Swap on write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mem_access.s.nsr = 0; /* No-Snoop on read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mem_access.s.nsw = 0; /* No-Snoop on write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mem_access.s.ror = 0; /* Relax Read on read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mem_access.s.row = 0; /* Relax Order on write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Remap the Octeon BAR 2 above all 32 bit devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * (0x8000000000ul). This is done here so it is remapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * before the readl()'s below. We don't want BAR2 overlapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * with BAR0/BAR1 during these reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) octeon_npi_write32(CVMX_NPI_PCI_CFG08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) octeon_npi_write32(CVMX_NPI_PCI_CFG09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Remap the Octeon BAR 0 to 0-2GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * BAR 1 hole).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* BAR1 movable mappings set for identity mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) octeon_bar1_pci_phys = 0x80000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (index = 0; index < 32; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) union cvmx_pci_bar1_indexx bar1_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bar1_index.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Address bits[35:22] sent to L2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) bar1_index.s.addr_idx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) (octeon_bar1_pci_phys >> 22) + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Don't put PCI accesses in L2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bar1_index.s.ca = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Endian Swap Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bar1_index.s.end_swp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Set '1' when the selected address range is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bar1_index.s.addr_v = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) bar1_index.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Devices go after BAR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) octeon_pci_mem_resource.start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) octeon_pci_mem_resource.end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) octeon_pci_mem_resource.start + (1ul << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Remap the Octeon BAR 1 to map 0-128MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* BAR1 movable regions contiguous to cover the swiotlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) octeon_bar1_pci_phys =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) for (index = 0; index < 32; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) union cvmx_pci_bar1_indexx bar1_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) bar1_index.u32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Address bits[35:22] sent to L2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bar1_index.s.addr_idx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (octeon_bar1_pci_phys >> 22) + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Don't put PCI accesses in L2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) bar1_index.s.ca = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Endian Swap Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) bar1_index.s.end_swp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Set '1' when the selected address range is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) bar1_index.s.addr_v = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bar1_index.u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Devices go after BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) octeon_pci_mem_resource.start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (4ul << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) octeon_pci_mem_resource.end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) octeon_pci_mem_resource.start + (1ul << 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) register_pci_controller(&octeon_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Clear any errors that might be pending from before the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * was setup properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) -1, NULL, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pr_err("Registration of co_pci_edac failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) octeon_pci_dma_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) arch_initcall(octeon_pci_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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