Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Ralink MT7620A SoC PCI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach-ralink/ralink_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mach-ralink/mt7620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RALINK_PCI_IO_MAP_BASE		0x10160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RALINK_PCI_MEMORY_BASE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RALINK_INT_PCIE0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RALINK_CLKCFG1			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RALINK_GPIOMODE			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PPLL_CFG1			0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PPLL_LD				BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PPLL_DRV			0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PDRV_SW_SET			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LC_CKDRVPD			BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LC_CKDRVOHZ			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LC_CKDRVHZ			BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LC_CKTEST			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* PCI Bridge registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RALINK_PCI_PCICFG_ADDR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCIRST				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RALINK_PCI_PCIENA		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCIINT2				BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RALINK_PCI_CONFIG_ADDR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RALINK_PCI_CONFIG_DATA_VIRT_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RALINK_PCI_MEMBASE		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RALINK_PCI_IOBASE		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* PCI RC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RALINK_PCI0_BAR0SETUP_ADDR	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RALINK_PCI0_IMBASEBAR0_ADDR	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RALINK_PCI0_ID			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RALINK_PCI0_CLASS		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RALINK_PCI0_SUBID		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RALINK_PCI0_STATUS		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCIE_LINK_UP_ST			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PCIEPHY0_CFG			0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RALINK_PCIEPHY_P0_CTL_OFFSET	0x7498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RALINK_PCIE0_CLK_EN		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BUSY				0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WAITRETRY_MAX			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WRITE_MODE			(1UL << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DATA_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ADDR_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void __iomem *bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void __iomem *pcie_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct reset_control *rstpcie0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline void bridge_w32(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	iowrite32(val, bridge_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static inline u32 bridge_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return ioread32(bridge_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static inline void pcie_w32(u32 val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	iowrite32(val, pcie_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static inline u32 pcie_r32(unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return ioread32(pcie_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 val = pcie_r32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	val &= ~clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	pcie_w32(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int wait_pciephy_busy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long reg_value = 0x0, retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		reg_value = pcie_r32(PCIEPHY0_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (reg_value & BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (retry++ > WAITRETRY_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			pr_warn("PCIE-PHY retry failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void pcie_phy(unsigned long addr, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	wait_pciephy_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		 PCIEPHY0_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	wait_pciephy_busy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			   int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8 func = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		num = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		  (func << 8) | (where & 0xfc) | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		*val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			    int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u8 func = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u32 num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		num = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		  (func << 8) | (where & 0xfc) | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			(val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			(val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pci_ops mt7620_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.read	= pci_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.write	= pci_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct resource mt7620_res_pci_mem1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct resource mt7620_res_pci_io1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct pci_controller mt7620_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.pci_ops	= &mt7620_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.mem_resource	= &mt7620_res_pci_mem1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.mem_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.io_resource	= &mt7620_res_pci_io1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.io_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.io_map_base	= 0xa0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int mt7620_pci_hw_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* bypass PCIe DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	pcie_phy(0x0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	pcie_phy(0x1, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Elastic buffer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	pcie_phy(0x68, 0xB4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* put core into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	reset_control_assert(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* disable power and all clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* bring core out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	reset_control_deassert(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		reset_control_assert(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* power up the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		    PPLL_DRV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int mt7628_pci_hw_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* bring the core out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	reset_control_deassert(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* enable the pci clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* voodoo from the SDK driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	pci_config_read(NULL, 0, 0x70c, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	val &= ~(0xff) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	val |= 0x50 << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	pci_config_write(NULL, 0, 0x70c, 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	pci_config_read(NULL, 0, 0x70c, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int mt7620_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct resource *bridge_res = platform_get_resource(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 							    IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct resource *pcie_res = platform_get_resource(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 							  IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (IS_ERR(rstpcie0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return PTR_ERR(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (IS_ERR(bridge_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return PTR_ERR(bridge_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (IS_ERR(pcie_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return PTR_ERR(pcie_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	iomem_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	iomem_resource.end = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ioport_resource.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ioport_resource.end = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* bring up the pci core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	switch (ralink_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	case MT762X_SOC_MT7620A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (mt7620_pci_hw_init(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case MT762X_SOC_MT7628AN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	case MT762X_SOC_MT7688:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		if (mt7628_pci_hw_init(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	mdelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* enable write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* check if there is a card present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		reset_control_assert(rstpcie0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if (ralink_soc == MT762X_SOC_MT7620A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* setup ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	pcie_w32(0x06040001, RALINK_PCI0_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* voodoo from the SDK driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	pci_config_read(NULL, 0, 4, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	pci_config_write(NULL, 0, 4, 4, val | 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	register_pci_controller(&mt7620_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if ((dev->bus->number == 0) && (slot == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				 RALINK_PCI_MEMORY_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		irq = RALINK_INT_PCIE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			dev->bus->number, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dev->bus->number, slot, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/* configure the cache line size to 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* configure latency timer to 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	/* setup the slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct of_device_id mt7620_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ .compatible = "mediatek,mt7620-pci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct platform_driver mt7620_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.probe = mt7620_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.name = "mt7620-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.of_match_table = of_match_ptr(mt7620_pci_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int __init mt7620_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	return platform_driver_register(&mt7620_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) arch_initcall(mt7620_pci_init);