^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Carsten Langgaard <carstenl@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MIPS boards specific PCI support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/gt64120.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mips-boards/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mips-boards/bonito64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mips-boards/msc01_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct resource bonito64_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .name = "Bonito PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct resource bonito64_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "Bonito PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .start = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .end = 0x000fffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct resource gt64120_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .name = "GT-64120 PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct resource gt64120_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "GT-64120 PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct resource msc_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .name = "MSC PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct resource msc_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "MSC PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern struct pci_ops bonito64_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern struct pci_ops gt64xxx_pci0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern struct pci_ops msc_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct pci_controller bonito64_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pci_ops = &bonito64_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .io_resource = &bonito64_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .mem_resource = &bonito64_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .io_offset = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct pci_controller gt64120_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pci_ops = >64xxx_pci0_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .io_resource = >64120_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .mem_resource = >64120_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct pci_controller msc_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pci_ops = &msc_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .io_resource = &msc_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .mem_resource = &msc_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __init mips_pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pci_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) switch (mips_revision_sconid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case MIPS_REVISION_SCON_GT64120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Due to a bug in the Galileo system controller, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * to setup the PCI BAR for the Galileo internal registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This should be done in the bios/bootprom and will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * fixed in a later revision of YAMON (the MIPS boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * boot prom).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GT_WRITE(GT_PCI0_CFGADDR_OFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GT_PCI0_CFGADDR_CONFIGEN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Perform the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Set up resource ranges from the controller's registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) start = GT_READ(GT_PCI0M0LD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) end = GT_READ(GT_PCI0M0HD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) map = GT_READ(GT_PCI0M0REMAP_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) start1 = GT_READ(GT_PCI0M1LD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) end1 = GT_READ(GT_PCI0M1HD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) map1 = GT_READ(GT_PCI0M1REMAP_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Cannot support multiple windows, use the wider. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (end1 - start1 > end - start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) start = start1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) end = end1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) map = map1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mask = ~(start ^ end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* We don't support remapping with a discontiguous mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mask != ~((mask & -mask) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gt64120_mem_resource.start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gt64120_mem_resource.end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gt64120_controller.mem_offset = (start & mask) - (map & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Addresses are 36-bit, so do shifts in the destinations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) start = GT_READ(GT_PCI0IOLD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) end = GT_READ(GT_PCI0IOHD_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) map = GT_READ(GT_PCI0IOREMAP_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mask = ~(start ^ end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* We don't support remapping with a discontiguous mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mask != ~((mask & -mask) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gt64120_io_resource.start = map & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gt64120_io_resource.end = (map & mask) | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gt64120_controller.io_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Addresses are 36-bit, so do shifts in the destinations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) controller = >64120_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case MIPS_REVISION_SCON_BONITO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Set up resource ranges from the controller's registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) map = BONITO_PCIMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Combine as many adjacent windows as possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) map = map1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) start = BONITO_PCILO0_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) end = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (map3 == map2 + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) map = map2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) start = BONITO_PCILO1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) end++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (map2 == map1 + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) map = map1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) start = BONITO_PCILO0_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) end++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bonito64_mem_resource.start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bonito64_mem_resource.end = start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BONITO_PCIMAP_WINBASE(end) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bonito64_controller.mem_offset = start -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BONITO_PCIMAP_WINBASE(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) controller = &bonito64_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case MIPS_REVISION_SCON_SOCIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case MIPS_REVISION_SCON_ROCIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case MIPS_REVISION_SCON_SOCITSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case MIPS_REVISION_SCON_SOCITSCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Set up resource ranges from the controller's registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MSC_READ(MSC01_PCI_SC2PMBASL, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MSC_READ(MSC01_PCI_SC2PMMAPL, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) msc_mem_resource.start = start & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) msc_mem_resource.end = (start & mask) | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msc_controller.mem_offset = (start & mask) - (map & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (mips_cps_numiocu(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) write_gcr_reg0_base(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) write_gcr_reg0_mask(mask |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CM_GCR_REGn_MASK_CMTGT_IOCU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MSC_READ(MSC01_PCI_SC2PIOBASL, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) msc_io_resource.start = map & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msc_io_resource.end = (map & mask) | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msc_controller.io_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ioport_resource.end = ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (mips_cps_numiocu(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) write_gcr_reg1_base(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) write_gcr_reg1_mask(mask |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CM_GCR_REGn_MASK_CMTGT_IOCU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* If ranges overlap I/O takes precedence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) start = start & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) end = start | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if ((start >= msc_mem_resource.start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) start <= msc_mem_resource.end) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (end >= msc_mem_resource.start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) end <= msc_mem_resource.end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Use the larger space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) start = max(start, msc_mem_resource.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) end = min(end, msc_mem_resource.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (start - msc_mem_resource.start >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) msc_mem_resource.end - end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) msc_mem_resource.end = start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) msc_mem_resource.start = end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) controller = &msc_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* PIIX4 ACPI starts at 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (controller->io_resource->start < 0x00001000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) controller->io_resource->start = 0x00001000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ioport_resource.end = controller->io_resource->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) controller->io_map_base = mips_io_port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) register_pci_controller(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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