Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <lantiq_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "pci-lantiq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PCI_CR_FCI_ADDR_MAP0		0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_CR_FCI_ADDR_MAP1		0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCI_CR_FCI_ADDR_MAP2		0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCI_CR_FCI_ADDR_MAP3		0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCI_CR_FCI_ADDR_MAP4		0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PCI_CR_FCI_ADDR_MAP5		0x00D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCI_CR_FCI_ADDR_MAP6		0x00D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCI_CR_FCI_ADDR_MAP7		0x00DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PCI_CR_CLK_CTRL			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCI_CR_PCI_MOD			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCI_CR_PC_ARB			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCI_CR_FCI_ADDR_MAP11hg		0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PCI_CR_BAR11MASK		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCI_CR_BAR12MASK		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCI_CR_BAR13MASK		0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCI_CS_BASE_ADDR1		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PCI_CR_PCI_ADDR_MAP11		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCI_CR_FCI_BURST_LENGTH		0x00E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCI_CR_PCI_EOI			0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCI_CS_STS_CMD			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCI_MASTER0_REQ_MASK_2BITS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCI_MASTER1_REQ_MASK_2BITS	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCI_MASTER2_REQ_MASK_2BITS	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define INTERNAL_ARB_ENABLE_BIT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LTQ_CGU_IFCCR		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LTQ_CGU_PCICR		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ltq_pci_w32(x, y)	ltq_w32((x), ltq_pci_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ltq_pci_r32(x)		ltq_r32(ltq_pci_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ltq_pci_cfg_w32(x, y)	ltq_w32((x), ltq_pci_mapped_cfg + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ltq_pci_cfg_r32(x)	ltq_r32(ltq_pci_mapped_cfg + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) __iomem void *ltq_pci_mapped_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static __iomem void *ltq_pci_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static struct clk *clk_pci, *clk_external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct resource pci_io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct resource pci_mem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static struct pci_ops pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.read	= ltq_pci_read_config_dword,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.write	= ltq_pci_write_config_dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static struct pci_controller pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.pci_ops	= &pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.mem_resource	= &pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.mem_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.io_resource	= &pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.io_offset	= 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static inline u32 ltq_calc_bar11mask(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 mem, bar11mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* BAR11MASK value depends on available memory on system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mem = get_num_physpages() * PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return bar11mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int ltq_pci_startup(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	const __be32 *req_mask, *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 temp_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* get our clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	clk_pci = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (IS_ERR(clk_pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		dev_err(&pdev->dev, "failed to get pci clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return PTR_ERR(clk_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	clk_external = clk_get(&pdev->dev, "external");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (IS_ERR(clk_external)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		clk_put(clk_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_err(&pdev->dev, "failed to get external pci clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return PTR_ERR(clk_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* read the bus speed that we want */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (bus_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		clk_set_rate(clk_pci, *bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* and enable the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	clk_enable(clk_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (of_find_property(node, "lantiq,external-clock", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		clk_enable(clk_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		clk_disable(clk_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* setup reset gpio used by pci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (gpio_is_valid(reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		int ret = devm_gpio_request(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 						reset_gpio, "pci-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				"failed to request gpio %d\n", reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		gpio_direction_output(reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* enable auto-switching between PCI and EBU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* busy, i.e. configuration is not done, PCI access has to be retried */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* BUS Master/IO/MEM access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* enable external 2 PCI masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* setup the request mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	req_mask = of_get_property(node, "req-mask", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (req_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		temp_buffer &= ~((*req_mask & 0xf) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		temp_buffer &= ~0xf0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* enable internal arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* enable internal PCI master reqest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* enable EBU request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* enable all external masters request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* setup BAR memory regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* both TX and RX endian swap are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		PCI_CR_BAR12MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		PCI_CR_BAR13MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/*use 8 dw burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* setup irq line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* toggle reset pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (gpio_is_valid(reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		__gpio_set_value(reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		__gpio_set_value(reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int ltq_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct resource *res_cfg, *res_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	pci_clear_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (IS_ERR(ltq_pci_membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return PTR_ERR(ltq_pci_membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (IS_ERR(ltq_pci_mapped_cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return PTR_ERR(ltq_pci_mapped_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ltq_pci_startup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	register_pci_controller(&pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct of_device_id ltq_pci_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ .compatible = "lantiq,pci-xway" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct platform_driver ltq_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.probe = ltq_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.name = "pci-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.of_match_table = ltq_pci_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int ret = platform_driver_register(&ltq_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pr_info("pci-xway: Error registering platform driver!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) arch_initcall(pcibios_init);