^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000, 2001 Keith M Wesolowski
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ip32/mace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/ip32/ip32_ints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #undef DEBUG_MACE_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Handle errors from the bridge. This includes master and target aborts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * various command and address errors, and the interrupt test. This gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * registered on the bridge error irq. It's conceivable that some of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * conditions warrant a panic. Anybody care to say which ones?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static irqreturn_t macepci_error(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) char s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int flags = mace->pci.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int addr = mace->pci.error_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (flags & MACEPCI_ERROR_MEMORY_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) s = 'M';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) else if (flags & MACEPCI_ERROR_CONFIG_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) s = 'C';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) s = 'X';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (flags & MACEPCI_ERROR_MASTER_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) printk("MACEPCI: Master abort at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) flags &= ~MACEPCI_ERROR_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (flags & MACEPCI_ERROR_TARGET_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) printk("MACEPCI: Target abort at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) flags &= ~MACEPCI_ERROR_TARGET_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) printk("MACEPCI: Data parity error at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) flags &= ~MACEPCI_ERROR_DATA_PARITY_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (flags & MACEPCI_ERROR_RETRY_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) printk("MACEPCI: Retry error at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) flags &= ~MACEPCI_ERROR_RETRY_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (flags & MACEPCI_ERROR_ILLEGAL_CMD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) printk("MACEPCI: Illegal command at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) flags &= ~MACEPCI_ERROR_ILLEGAL_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (flags & MACEPCI_ERROR_SYSTEM_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) printk("MACEPCI: System error at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) flags &= ~MACEPCI_ERROR_SYSTEM_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (flags & MACEPCI_ERROR_PARITY_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) printk("MACEPCI: Parity error at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) flags &= ~MACEPCI_ERROR_PARITY_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (flags & MACEPCI_ERROR_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) printk("MACEPCI: Overrun error at 0x%08x (%c)\n", addr, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) flags &= ~MACEPCI_ERROR_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (flags & MACEPCI_ERROR_SIG_TABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) printk("MACEPCI: Signaled target abort (clearing)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) flags &= ~MACEPCI_ERROR_SIG_TABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (flags & MACEPCI_ERROR_INTERRUPT_TEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) printk("MACEPCI: Interrupt test triggered (clearing)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) flags &= ~MACEPCI_ERROR_INTERRUPT_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mace->pci.error = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern struct pci_ops mace_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct resource mace_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "SGI O2 PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .start = MACEPCI_HI_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .end = 0x2FFFFFFFFUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct resource mace_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .name = "SGI O2 PCI IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .start = 0x00000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .end = 0xffffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MACE_PCI_MEM_OFFSET 0x200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct resource mace_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "SGI O2 PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .start = MACEPCI_LOW_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .end = MACEPCI_LOW_MEMORY + 0x2000000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct resource mace_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "SGI O2 PCI IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .start = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .end = 0xFFFFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MACE_PCI_MEM_OFFSET (MACEPCI_LOW_MEMORY - 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct pci_controller mace_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pci_ops = &mace_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .mem_resource = &mace_pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .io_resource = &mace_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .mem_offset = MACE_PCI_MEM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .io_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int __init mace_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PCIBIOS_MIN_IO = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Clear any outstanding errors and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mace->pci.error_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mace->pci.error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mace->pci.control = 0xff008500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) printk("MACE PCI rev %d\n", mace->pci.rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "MACE PCI error", NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* extend memory resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iomem_resource.end = mace_pci_mem_resource.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ioport_resource = mace_pci_io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) register_pci_controller(&mace_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) arch_initcall(mace_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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