Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <bcm63xx_reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "pci-bcm63xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Allow PCI to be disabled at runtime depending on board nvram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) int bcm63xx_pci_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static struct resource bcm_pci_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.name	= "bcm63xx PCI memory space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.start	= BCM_PCI_MEM_BASE_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.end	= BCM_PCI_MEM_END_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.flags	= IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static struct resource bcm_pci_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.name	= "bcm63xx PCI IO space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.start	= BCM_PCI_IO_BASE_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifdef CONFIG_CARDBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.end	= BCM_PCI_IO_HALF_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.end	= BCM_PCI_IO_END_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.flags	= IORESOURCE_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct pci_controller bcm63xx_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.pci_ops	= &bcm63xx_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.io_resource	= &bcm_pci_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.mem_resource	= &bcm_pci_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * We handle cardbus  via a fake Cardbus bridge,  memory and io spaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * have to be  clearly separated from PCI one  since we have different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * memory decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #ifdef CONFIG_CARDBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct resource bcm_cb_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.name	= "bcm63xx Cardbus memory space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.start	= BCM_CB_MEM_BASE_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.end	= BCM_CB_MEM_END_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.flags	= IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct resource bcm_cb_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.name	= "bcm63xx Cardbus IO space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.start	= BCM_PCI_IO_HALF_PA + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.end	= BCM_PCI_IO_END_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.flags	= IORESOURCE_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct pci_controller bcm63xx_cb_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.pci_ops	= &bcm63xx_cb_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.io_resource	= &bcm_cb_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.mem_resource	= &bcm_cb_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct resource bcm_pcie_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.name	= "bcm63xx PCIe memory space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.start	= BCM_PCIE_MEM_BASE_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.end	= BCM_PCIE_MEM_END_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct resource bcm_pcie_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.name	= "bcm63xx PCIe IO space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.start	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.end	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) struct pci_controller bcm63xx_pcie_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.pci_ops	= &bcm63xx_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.io_resource	= &bcm_pcie_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.mem_resource	= &bcm_pcie_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static u32 bcm63xx_int_cfg_readl(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return bcm_mpi_readl(MPI_PCICFGDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	tmp |=	MPI_PCICFGCTL_WRITEEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void __iomem *pci_iospace_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void __init bcm63xx_reset_pcie(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* enable SERDES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (BCMCPU_IS_6328())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		reg = MISC_SERDES_CTRL_6328_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		reg = MISC_SERDES_CTRL_6362_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	val = bcm_misc_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	bcm_misc_writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* reset the PCIe core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mdelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct clk *pcie_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __init bcm63xx_register_pcie(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	pcie_clk = clk_get(NULL, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (IS_ERR_OR_NULL(pcie_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	clk_prepare_enable(pcie_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	bcm63xx_reset_pcie();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* configure the PCIe bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	val |= OPT1_RD_BE_OPT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	val |= OPT1_RD_REPLY_BE_FIX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	val |= OPT1_L1_INT_STATUS_MASK_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* setup the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* enable credit checking and error checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	val |= OPT2_TX_CREDIT_CHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	val |= OPT2_UBUS_UR_DECODE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* set device bus/func for the pcie device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	val |= OPT2_CFG_TYPE1_BD_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* setup class code as bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	val = bcm_pcie_readl(PCIE_IDVAL3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	val &= ~IDVAL3_CLASS_CODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	bcm_pcie_writel(val, PCIE_IDVAL3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* disable bar1 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	val = bcm_pcie_readl(PCIE_CONFIG2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	val &= ~CONFIG2_BAR1_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* set bar0 to little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	val |= BASEMASK_REMAP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	register_pci_controller(&bcm63xx_pcie_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init bcm63xx_register_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned int mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * configuration  access are  done through  IO space,  remap 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * first bytes to access it from CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * this means that  no io access from CPU  should happen while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * we do a configuration cycle,	 but there's no way we can add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * a spinlock for each io access, so this is currently kind of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * broken on SMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	pci_iospace_start = ioremap(BCM_PCI_IO_BASE_PA, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!pci_iospace_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* setup local bus to PCI access (PCI memory) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* set Cardbus IDSEL (type 0 cfg access on primary bus for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * this IDSEL will be done on Cardbus instead) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	val = bcm_pcmcia_readl(PCMCIA_C1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	val &= ~PCMCIA_C1_CBIDSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	bcm_pcmcia_writel(val, PCMCIA_C1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_CARDBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* setup local bus to PCI access (Cardbus memory) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* disable second access windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* setup local bus  to PCI access (IO memory),	we have only 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * IO window  for both PCI  and cardbus, but it	 cannot handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * both	 at the	 same time,  assume standard  PCI for  now, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * cardbus card has  IO zone, PCI fixup will  change window to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * cardbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* enable PCI related GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* setup PCI to local bus access, used by PCI device to target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * local RAM while bus mastering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		val = MPI_SP0_REMAP_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mem_size = bcm63xx_get_memory_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* 6348 before rev b0 exposes only 16 MB of RAM memory through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * PCI, throw a warning if we have more memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (mem_size > (16 * 1024 * 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			printk(KERN_WARNING "bcm63xx: this CPU "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			       "revision cannot handle more than 16MB "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			       "of RAM for PCI bus mastering\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		/* setup sp0 range to local RAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* change  host bridge	retry  counter to  infinite number  of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 * retry,  needed for  some broadcom  wifi cards  with Silicon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * Backplane bus where access to srom seems very slow  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	val &= ~REG_TIMER_RETRY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* enable memory decoder and bus mastering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	val = bcm63xx_int_cfg_readl(PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	bcm63xx_int_cfg_writel(val, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* enable read prefetching & disable byte swapping for bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * mastering transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* enable pci interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	val = bcm_mpi_readl(MPI_LOCINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	bcm_mpi_writel(val, MPI_LOCINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	register_pci_controller(&bcm63xx_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_CARDBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	register_pci_controller(&bcm63xx_cb_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* mark memory space used for IO mapping as reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			   "bcm63xx PCI IO space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int __init bcm63xx_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!bcm63xx_pci_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	switch (bcm63xx_get_cpu_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	case BCM6328_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	case BCM6362_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return bcm63xx_register_pcie();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	case BCM3368_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	case BCM6348_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	case BCM6358_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	case BCM6368_CPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return bcm63xx_register_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) arch_initcall(bcm63xx_pci_init);