^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001,2002,2005 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * BCM1480/1455-specific HT support (looking like PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This module provides the glue between Linux's PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and the hardware. We basically provide glue for accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * configuration space, and set up the translation for I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * space accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * To access configuration space, we use ioremap. In the 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * kernel, this consumes either 4 or 8 page table pages, and 16MB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * kernel mapped memory. Hopefully neither of these should be a huge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/sibyte/bcm1480_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/sibyte/bcm1480_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/sibyte/board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Macros for calculating offsets into config space given a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * structure or dev/fun/reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void *ht_cfg_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_BUS_ENABLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int bcm1480ht_bus_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_BRIDGE_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HT_BRIDGE_DEVICE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * HT's level-sensitive interrupts require EOI, which is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * through a 4MB memory-mapped region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long ht_eoi_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Read/write 32-bit values in config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline u32 READCFG32(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return *(u32 *)(ht_cfg_space + (addr&~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void WRITECFG32(u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *(u32 *)(ht_cfg_space + (addr & ~3)) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Some checks before doing config cycles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * In PCI Device Mode, hide everything on bus 0 except the LDT host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * bridge. Otherwise, access is controlled by bridge MasterEn bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) devno = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (bcm1480ht_bus_status & PCI_DEVICE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Read/write access functions for various sizes of values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * in config space. Return all 1's for disallowed accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * for a kludgy but adequate simulation of master aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (bcm1480ht_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) data = READCFG32(CFGADDR(bus, devfn, where));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) data = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 cfgaddr = CFGADDR(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!bcm1480ht_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data = READCFG32(cfgaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) WRITECFG32(cfgaddr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int bcm1480ht_pcibios_get_busno(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pci_ops bcm1480ht_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .read = bcm1480ht_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .write = bcm1480ht_pcibios_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct resource bcm1480ht_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "BCM1480 HT MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .start = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .end = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct resource bcm1480ht_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "BCM1480 HT I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .start = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .end = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct pci_controller bcm1480ht_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .pci_ops = &bcm1480ht_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .mem_resource = &bcm1480ht_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .io_resource = &bcm1480ht_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .get_busno = bcm1480ht_pcibios_get_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init bcm1480ht_pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* CFE doesn't always init all HT paths, so we always scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bcm1480ht_bus_status |= PCI_BUS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ht_eoi_space = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 4 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bcm1480ht_controller.io_map_base = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) register_pci_controller(&bcm1480ht_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) arch_initcall(bcm1480ht_pcibios_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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