^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001,2002,2005 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * BCM1x80/1x55-specific PCI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This module provides the glue between Linux's PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and the hardware. We basically provide glue for accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * configuration space, and set up the translation for I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * space accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * To access configuration space, we use ioremap. In the 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * kernel, this consumes either 4 or 8 page table pages, and 16MB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * kernel mapped memory. Hopefully neither of these should be a huge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/vt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/sibyte/bcm1480_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/sibyte/bcm1480_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/sibyte/board.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Macros for calculating offsets into config space given a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * structure or dev/fun/reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void *cfg_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_BUS_ENABLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DEVICE_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int bcm1480_bus_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_BRIDGE_DEVICE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Read/write 32-bit values in config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline u32 READCFG32(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return *(u32 *)(cfg_space + (addr&~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void WRITECFG32(u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *(u32 *)(cfg_space + (addr & ~3)) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (pin == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return K_BCM1480_INT_PCI_INTA - 1 + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Some checks before doing config cycles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * In PCI Device Mode, hide everything on bus 0 except the LDT host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * bridge. Otherwise, access is controlled by bridge MasterEn bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) devno = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (bcm1480_bus_status & PCI_DEVICE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Read/write access functions for various sizes of values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * in config space. Return all 1's for disallowed accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * for a kludgy but adequate simulation of master aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (bcm1480_pci_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) data = READCFG32(CFGADDR(bus, devfn, where));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 cfgaddr = CFGADDR(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!bcm1480_pci_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) data = READCFG32(cfgaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) WRITECFG32(cfgaddr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct pci_ops bcm1480_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .read = bcm1480_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .write = bcm1480_pcibios_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct resource bcm1480_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "BCM1480 PCI MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct resource bcm1480_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "BCM1480 PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pci_controller bcm1480_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .pci_ops = &bcm1480_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mem_resource = &bcm1480_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .io_resource = &bcm1480_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init bcm1480_pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) uint32_t cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint64_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* CFE will assign PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Avoid ISA compat ranges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PCIBIOS_MIN_IO = 0x00008000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PCIBIOS_MIN_MEM = 0x01000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Set I/O resource limits. - unlimited for now to accommodate HT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ioport_resource.end = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) iomem_resource.end = 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * See if the PCI bus has been configured by the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bcm1480_bus_status |= PCI_DEVICE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PCI_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!(cmdreg & PCI_COMMAND_MASTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ("PCI: Skipping PCI probe. Bus is not initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) iounmap(cfg_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 1; /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bcm1480_bus_status |= PCI_BUS_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* turn on ExpMemEn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cmdreg | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * space. Use "match bytes" policy to make everything look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * little-endian. So, you need to also set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * CONFIG_SWAP_IO_SPACE, but this is the combination that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * works correctly with most of Linux's drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * XXX ehs: Should this happen in PCI Device mode?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bcm1480_controller.io_map_base = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) set_io_port_base(bcm1480_controller.io_map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) register_pci_controller(&bcm1480_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_VGA_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) console_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) console_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) arch_initcall(bcm1480_pcibios_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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