^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atheros AR724X PCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AR724X_PCI_REG_APP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AR724X_PCI_REG_RESET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AR724X_PCI_REG_INT_STATUS 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AR724X_PCI_REG_INT_MASK 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AR724X_PCI_RESET_LINK_UP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AR724X_PCI_INT_DEV0 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AR724X_PCI_IRQ_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AR7240_BAR0_WAR_VALUE 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PCI_COMMAND_MASTER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PCI_COMMAND_INVALIDATE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PCI_COMMAND_PARITY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PCI_COMMAND_SERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PCI_COMMAND_FAST_BACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ar724x_pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *devcfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *crp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool link_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool bar0_is_cached;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 bar0_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pci_controller pci_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct resource io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct resource mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return reset & AR724X_PCI_RESET_LINK_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline struct ar724x_pci_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pci_bus_to_ar724x_controller(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) hose = (struct pci_controller *) bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return container_of(hose, struct ar724x_pci_controller, pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) WARN_ON(where & (size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!apc->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) base = apc->crp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data = __raw_readl(base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) s = ((where & 3) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) data &= ~(0xff << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) data |= ((value & 0xff) << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) s = ((where & 2) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) data &= ~(0xffff << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) data |= ((value & 0xffff) << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __raw_writel(data, base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __raw_readl(base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int size, uint32_t *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) apc = pci_bus_to_ar724x_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!apc->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) base = apc->devcfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data = __raw_readl(base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (where & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (where & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) data &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (where & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) data >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) apc->bar0_is_cached) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* use the cached value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *value = apc->bar0_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *value = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int size, uint32_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) apc = pci_bus_to_ar724x_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!apc->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (value != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * WAR for a hw issue. If the BAR0 register of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * device is set to the proper base address, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * memory space of the device is not accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Cache the intended value so it can be read back,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * and write a SoC specific constant value to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * BAR0 register in order to make the device memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) apc->bar0_is_cached = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) apc->bar0_value = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) value = AR7240_BAR0_WAR_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) apc->bar0_is_cached = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) base = apc->devcfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data = __raw_readl(base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) s = ((where & 3) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data &= ~(0xff << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) data |= ((value & 0xff) << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) s = ((where & 2) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data &= ~(0xffff << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) data |= ((value & 0xffff) << s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) data = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __raw_writel(data, base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __raw_readl(base + (where & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct pci_ops ar724x_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .read = ar724x_pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .write = ar724x_pci_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void ar724x_pci_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) apc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) base = apc->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (pending & AR724X_PCI_INT_DEV0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) generic_handle_irq(apc->irq_base + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void ar724x_pci_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) base = apc->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) offset = apc->irq_base - d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __raw_writel(t | AR724X_PCI_INT_DEV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void ar724x_pci_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) base = apc->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) offset = apc->irq_base - d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __raw_writel(t & ~AR724X_PCI_INT_DEV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __raw_writel(t | AR724X_PCI_INT_DEV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) base + AR724X_PCI_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static struct irq_chip ar724x_pci_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "AR724X PCI ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .irq_mask = ar724x_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .irq_unmask = ar724x_pci_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .irq_mask_ack = ar724x_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) base = apc->ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = apc->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) irq_set_chip_data(i, apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 ppl, app;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* deassert PCIe host controller and PCIe PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ath79_device_reset_clear(AR724X_RESET_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* remove the reset of the PCIE PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* deassert bypass for the PCIE PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* set PCIE Application Control to ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) app |= AR724X_PCI_APP_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* wait up to 100ms for PHY link up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) wait++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } while (wait < 10 && !ar724x_pci_check_link(apc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int ar724x_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct ar724x_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (id == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) apc->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "ctrl_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (IS_ERR(apc->ctrl_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return PTR_ERR(apc->ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) apc->devcfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(apc->devcfg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return PTR_ERR(apc->devcfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) apc->crp_base = devm_platform_ioremap_resource_byname(pdev, "crp_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (IS_ERR(apc->crp_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return PTR_ERR(apc->crp_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) apc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (apc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) apc->io_res.parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) apc->io_res.name = "PCI IO space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) apc->io_res.start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) apc->io_res.end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) apc->io_res.flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) apc->mem_res.parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) apc->mem_res.name = "PCI memory space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) apc->mem_res.start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) apc->mem_res.end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) apc->mem_res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) apc->pci_controller.pci_ops = &ar724x_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) apc->pci_controller.io_resource = &apc->io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) apc->pci_controller.mem_resource = &apc->mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Do the full PCIE Root Complex Initialization Sequence if the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * host controller is in reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ar724x_pci_hw_init(apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) apc->link_up = ar724x_pci_check_link(apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!apc->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_warn(&pdev->dev, "PCIe link is down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ar724x_pci_irq_init(apc, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) register_pci_controller(&apc->pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct platform_driver ar724x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .probe = ar724x_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "ar724x-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int __init ar724x_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return platform_driver_register(&ar724x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) postcore_initcall(ar724x_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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