Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Atheros AR71xx PCI host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Parts of this file are based on Atheros' 2.6.15 BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mach-ath79/ar71xx_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mach-ath79/ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AR71XX_PCI_REG_CRP_AD_CBE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AR71XX_PCI_REG_CRP_WRDATA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AR71XX_PCI_REG_CRP_RDDATA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AR71XX_PCI_REG_CFG_AD		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AR71XX_PCI_REG_CFG_CBE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AR71XX_PCI_REG_CFG_WRDATA	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AR71XX_PCI_REG_CFG_RDDATA	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AR71XX_PCI_REG_PCI_ERR		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AR71XX_PCI_REG_PCI_ERR_ADDR	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AR71XX_PCI_REG_AHB_ERR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AR71XX_PCI_REG_AHB_ERR_ADDR	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AR71XX_PCI_CRP_CMD_WRITE	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AR71XX_PCI_CRP_CMD_READ		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AR71XX_PCI_CFG_CMD_READ		0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AR71XX_PCI_CFG_CMD_WRITE	0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AR71XX_PCI_INT_CORE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AR71XX_PCI_INT_DEV2		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AR71XX_PCI_INT_DEV1		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AR71XX_PCI_INT_DEV0		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AR71XX_PCI_IRQ_COUNT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct ar71xx_pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct pci_controller pci_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct resource io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct resource mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* Byte lane enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const u8 ar71xx_pci_ble_table[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{0x0, 0xf, 0xf, 0xf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{0xe, 0xd, 0xb, 0x7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{0xc, 0xf, 0x3, 0xf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{0xf, 0xf, 0xf, 0xf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static const u32 ar71xx_pci_read_mask[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	t = ar71xx_pci_ble_table[size & 3][where & 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	BUG_ON(t == 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	t <<= (local) ? 20 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				      int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (!bus->number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/* type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		      (where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		      (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static inline struct ar71xx_pci_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) pci_bus_to_ar71xx_controller(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	hose = (struct pci_controller *) bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	void __iomem *base = apc->cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 pci_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 ahb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (pci_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (!quiet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				"PCI", pci_err, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		/* clear PCI error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (ahb_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (!quiet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				"AHB", ahb_err, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* clear AHB error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		__raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return !!(ahb_err | pci_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					  int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	void __iomem *base = apc->cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 ad_cbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	value = value << (8 * (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	__raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					 unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 					 int where, int size, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	void __iomem *base = apc->cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	addr = ar71xx_pci_bus_addr(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	__raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		     base + AR71XX_PCI_REG_CFG_CBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return ar71xx_pci_check_error(apc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				  int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	void __iomem *base = apc->cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	data = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				     AR71XX_PCI_CFG_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ret = PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				   int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	void __iomem *base = apc->cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	value = value << (8 * (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				     AR71XX_PCI_CFG_CMD_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		ret = PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct pci_ops ar71xx_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.read	= ar71xx_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.write	= ar71xx_pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void ar71xx_pci_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct ar71xx_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	void __iomem *base = ath79_reset_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	apc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (pending & AR71XX_PCI_INT_DEV0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		generic_handle_irq(apc->irq_base + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	else if (pending & AR71XX_PCI_INT_DEV1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		generic_handle_irq(apc->irq_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	else if (pending & AR71XX_PCI_INT_DEV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		generic_handle_irq(apc->irq_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	else if (pending & AR71XX_PCI_INT_CORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		generic_handle_irq(apc->irq_base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void ar71xx_pci_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct ar71xx_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	void __iomem *base = ath79_reset_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	irq = d->irq - apc->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void ar71xx_pci_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct ar71xx_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	void __iomem *base = ath79_reset_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	irq = d->irq - apc->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct irq_chip ar71xx_pci_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.name		= "AR71XX PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.irq_mask	= ar71xx_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.irq_unmask	= ar71xx_pci_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.irq_mask_ack	= ar71xx_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	void __iomem *base = ath79_reset_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	apc->irq_base = ATH79_PCI_IRQ_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	for (i = apc->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		irq_set_chip_data(i, apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 					 apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void ar71xx_pci_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ath79_ddr_set_pci_windows();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int ar71xx_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct ar71xx_pci_controller *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	apc->cfg_base = devm_platform_ioremap_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 							      "cfg_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (IS_ERR(apc->cfg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return PTR_ERR(apc->cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	apc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (apc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	apc->io_res.parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	apc->io_res.name = "PCI IO space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	apc->io_res.start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	apc->io_res.end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	apc->io_res.flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	apc->mem_res.parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	apc->mem_res.name = "PCI memory space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	apc->mem_res.start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	apc->mem_res.end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	apc->mem_res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ar71xx_pci_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* setup COMMAND register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/* clear bus errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ar71xx_pci_check_error(apc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ar71xx_pci_irq_init(apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	apc->pci_ctrl.mem_resource = &apc->mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	apc->pci_ctrl.io_resource = &apc->io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	register_pci_controller(&apc->pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct platform_driver ar71xx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.probe = ar71xx_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		.name = "ar71xx-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int __init ar71xx_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return platform_driver_register(&ar71xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) postcore_initcall(ar71xx_pci_init);