^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * and interrupt. PCI interface supports MMIO access method, but does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * seem to support I/O ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * a memory read/write command on the PCI bus. 30 LSBs of address on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the bus are taken from memory read/write request and 2 MSBs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * determined by PCI unit configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * To work with the configuration space instead of memory is necessary set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the CFG_SEL bit in the PCI_MISC_CONFIG register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Devices on the bus can perform DMA requests via chip BAR1. PCI host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * controller BARs are programmend as if an external device is programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Which means that during configuration, IDSEL pin of the chip should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * We know (and support) only one board that uses the PCI interface -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * and IDSEL pin of AR2315 is connected to AD[16] line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/paccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * PCI Bus Interface Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AR2315_PCI_1MS_REG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AR2315_PCI_MISC_CONFIG 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AR2315_PCIMISC_RST_MODE 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AR2315_PCI_OUT_TSTAMP 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AR2315_PCI_UNCACHE_CFG 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AR2315_PCI_IN_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AR2315_PCI_IN_DIS 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AR2315_PCI_IN_PTR 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AR2315_PCI_OUT_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AR2315_PCI_OUT_DIS 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AR2315_PCI_OUT_PTR 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PCI interrupt status (write one to clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AR2315_PCI_ISR 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* PCI interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AR2315_PCI_IMR 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Global PCI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AR2315_PCI_IER 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AR2315_PCI_HOST_IN_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AR2315_PCI_HOST_IN_DIS 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AR2315_PCI_HOST_IN_PTR 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AR2315_PCI_HOST_OUT_EN 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AR2315_PCI_HOST_OUT_DIS 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AR2315_PCI_HOST_OUT_PTR 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * PCI interrupts, which share IP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Keep ordered according to AR2315_PCI_INT_XXX bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AR2315_PCI_IRQ_EXT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AR2315_PCI_IRQ_ABORT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AR2315_PCI_IRQ_COUNT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Arbitrary size of memory region to access the configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AR2315_PCI_CFG_SIZE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AR2315_PCI_HOST_SLOT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * We need some arbitrary non-zero value to be programmed to the BAR1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * of PCI host controller to enable DMA. The same value should be used as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * offset to calculate the physical address of DMA buffer for PCI devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* ??? access BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AR2315_PCI_HOST_MBAR0 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* RAM access BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* ??? access BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AR2315_PCI_HOST_MBAR2 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ar2315_pci_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *cfg_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *mmr_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned irq_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pci_controller pci_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct resource mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct resource io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline dma_addr_t ar2315_dev_offset(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (dev && dev_is_pci(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return AR2315_PCI_HOST_SDRAM_BASEADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return paddr + ar2315_dev_offset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return dma_addr - ar2315_dev_offset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct pci_controller *hose = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return __raw_readl(apc->mmr_mem + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __raw_writel(val, apc->mmr_mem + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 ret = ar2315_pci_reg_read(apc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ar2315_pci_reg_write(apc, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int where, int size, u32 *ptr, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int func = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 mask = 0xffffffff >> 8 * (4 - size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 sh = (where & 3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 value, isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Prevent access past the remapped area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Clear pending errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Select Configuration access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) AR2315_PCIMISC_CFG_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mb(); /* PCI must see space change before we begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) value = __raw_readl(apc->cfg_mem + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (isr & AR2315_PCI_INT_ABORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto exit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) value = (value & ~(mask << sh)) | *ptr << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __raw_writel(value, apc->cfg_mem + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (isr & AR2315_PCI_INT_ABORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto exit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *ptr = (value >> sh) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) exit_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *ptr = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Select Memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned devfn, int where, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned devfn, int where, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct pci_ops ar2315_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .read = ar2315_pci_cfg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .write = ar2315_pci_cfg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Program MBARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AR2315_PCI_HOST_MBAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AR2315_PCI_HOST_MBAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) AR2315_PCI_HOST_MBAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void ar2315_pci_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned pci_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (pci_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) generic_handle_irq(pci_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void ar2315_pci_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void ar2315_pci_irq_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 m = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void ar2315_pci_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct irq_chip ar2315_pci_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "AR2315-PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .irq_mask = ar2315_pci_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .irq_mask_ack = ar2315_pci_irq_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .irq_unmask = ar2315_pci_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) irq_set_chip_data(irq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .map = ar2315_pci_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) AR2315_PCI_INT_EXT), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Clear any pending Abort or external Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * and enable interrupt processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) AR2315_PCI_INT_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int ar2315_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct ar2315_pci_ctrl *apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!apc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) apc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "ar2315-pci-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(apc->mmr_mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return PTR_ERR(apc->mmr_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "ar2315-pci-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) apc->mem_res.name = "AR2315 PCI mem space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) apc->mem_res.parent = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) apc->mem_res.start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) apc->mem_res.end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) apc->mem_res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Remap PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) apc->cfg_mem = devm_ioremap(dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AR2315_PCI_CFG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!apc->cfg_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "failed to remap PCI config space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) AR2315_PCIMISC_RST_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AR2315_PCIRST_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Bring the PCI out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) AR2315_PCIMISC_RST_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x1E | /* 1GB uncached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) (1 << 5) | /* Enable uncached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) (0x2 << 30) /* Base: 0x80000000 */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) err = ar2315_pci_host_setup(apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &ar2315_pci_irq_domain_ops, apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!apc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(dev, "failed to add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ar2315_pci_irq_init(apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* PCI controller does not support I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) apc->io_res.name = "AR2315 IO space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) apc->io_res.start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) apc->io_res.end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) apc->io_res.flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) apc->pci_ctrl.mem_resource = &apc->mem_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) apc->pci_ctrl.io_resource = &apc->io_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) register_pci_controller(&apc->pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_info(dev, "register PCI controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct platform_driver ar2315_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .probe = ar2315_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .name = "ar2315-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int __init ar2315_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return platform_driver_register(&ar2315_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) arch_initcall(ar2315_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return slot ? 0 : apc->irq_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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