^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Alchemy PCI host mode support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Support for all devices (greater than 16) added by David Gathright.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma-coherence.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/tlbmisc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifdef CONFIG_PCI_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DBG(x...) printk(KERN_DEBUG x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DBG(x...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_ACCESS_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_ACCESS_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct alchemy_pci_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *regs; /* ctrl base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* tools for wired entry for config space access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long last_elo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long last_elo1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int wired_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct vm_struct *pci_cfg_vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long pm[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int (*board_pci_idsel)(unsigned int devsel, int assert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * should suffice for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct alchemy_pci_context *__alchemy_pci_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * in arch/mips/alchemy/common/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource alchemy_pci_def_memres = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .start = ALCHEMY_PCI_MEMWIN_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .end = ALCHEMY_PCI_MEMWIN_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "PCI memory space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct resource alchemy_pci_def_iores = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .start = ALCHEMY_PCI_IOWIN_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .end = ALCHEMY_PCI_IOWIN_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "PCI IO space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .flags = IORESOURCE_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void mod_wired_entry(int entry, unsigned long entrylo0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long entrylo1, unsigned long entryhi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long pagemask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long old_pagemask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long old_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Save old context and create impossible VPN2 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) old_ctx = read_c0_entryhi() & MIPS_ENTRYHI_ASID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) old_pagemask = read_c0_pagemask();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) write_c0_index(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) write_c0_pagemask(pagemask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) write_c0_entryhi(entryhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) write_c0_entrylo0(entrylo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) write_c0_entrylo1(entrylo1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) write_c0_entryhi(old_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) write_c0_pagemask(old_pagemask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ctx->wired_entry = read_c0_wired();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ctx->last_elo0 = ctx->last_elo1 = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int config_access(unsigned char access_type, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int dev_fn, unsigned char where, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct alchemy_pci_context *ctx = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int device = PCI_SLOT(dev_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int function = PCI_FUNC(dev_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int error = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (device > 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) r |= PCI_STATCMD_STATUS(0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Allow board vendors to implement their own off-chip IDSEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * If it doesn't succeed, may as well bail out at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ctx->board_pci_idsel(device, 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Setup the config window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (bus->number == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cfg_base = (1 << device) << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Setup the lower bits of the 36-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offset = (function << 8) | (where & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Pick up any address that falls below the page mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) offset |= cfg_base & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cfg_base = cfg_base & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* To improve performance, if the current device is the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the last device accessed, we don't touch the TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ctx->last_elo0 = entryLo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ctx->last_elo1 = entryLo1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (access_type == PCI_ACCESS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) access_type, bus->number, device, where, *data, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* check for errors, master abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (status & (1 << 29)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) error = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) access_type, bus->number, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } else if ((status >> 28) & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) device, (status >> 28) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *data = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) error = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Take away the IDSEL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (void)ctx->board_pci_idsel(device, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int where, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (where & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (where & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *val = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int read_config_word(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int where, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (where & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) data >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *val = data & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int where, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int where, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int write_config_word(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int where, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int where, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 1: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int rc = read_config_byte(bus, devfn, where, &_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *val = _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case 2: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int rc = read_config_word(bus, devfn, where, &_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *val = _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return read_config_dword(bus, devfn, where, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return write_config_byte(bus, devfn, where, (u8) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return write_config_word(bus, devfn, where, (u16) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return write_config_dword(bus, devfn, where, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct pci_ops alchemy_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .read = alchemy_pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .write = alchemy_pci_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* save PCI controller register contents. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int alchemy_pci_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void alchemy_pci_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * on resume, making it necessary to recreate it as soon as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ctx->wired_entry = 8191; /* impossibly high value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) alchemy_pci_wired_entry(ctx); /* install it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct syscore_ops alchemy_pci_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .suspend = alchemy_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .resume = alchemy_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int alchemy_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct alchemy_pci_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void __iomem *virt_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* need at least PCI IRQ mapping table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(&pdev->dev, "need platform data for PCI setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&pdev->dev, "no memory for pcictl context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&pdev->dev, "cannot claim pci regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) c = clk_get(&pdev->dev, "pci_clko");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(&pdev->dev, "unable to find PCI clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = PTR_ERR(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = clk_prepare_enable(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(&pdev->dev, "cannot enable PCI clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto out6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ctx->regs = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!ctx->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&pdev->dev, "cannot map pci regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto out5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* map parts of the PCI IO area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* REVISIT: if this changes with a newer variant (doubt it) make this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * a platform resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!virt_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(&pdev->dev, "cannot remap pci io space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Au1500 revisions older than AD have borked coherent PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) (read_c0_prid() < 0x01030202) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (coherentio == IO_COHERENCE_DISABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val |= PCI_CONFIG_NC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (pd->board_map_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ctx->board_map_irq = pd->board_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pd->board_pci_idsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ctx->board_pci_idsel = pd->board_pci_idsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ctx->board_pci_idsel = alchemy_pci_def_idsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* fill in relevant pci_controller members */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* we can't ioremap the entire pci config space because it's too large,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * nor can we dynamically ioremap it because some drivers use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * PCI config routines from within atomic contex and that becomes a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * problem in get_vm_area(). Instead we use one wired TLB entry to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * handle all config accesses for all busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!ctx->pci_cfg_vm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(&pdev->dev, "unable to get vm area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto out4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ctx->wired_entry = 8191; /* impossibly high value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) alchemy_pci_wired_entry(ctx); /* install it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* board may want to modify bits in the config register, do it now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val &= ~pd->pci_cfg_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val |= pd->pci_cfg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val &= ~PCI_CONFIG_PD; /* clear disable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __alchemy_pci_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) register_syscore_ops(&alchemy_pci_pmops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) register_pci_controller(&ctx->alchemy_pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_info(&pdev->dev, "PCI controller at %ld MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clk_get_rate(c) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) out4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) iounmap(virt_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) out3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) iounmap(ctx->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) out5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk_disable_unprepare(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) out6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_put(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) release_mem_region(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct platform_driver alchemy_pcictl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .probe = alchemy_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "alchemy-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int __init alchemy_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Au1500/Au1550 have PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (alchemy_get_cputype()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case ALCHEMY_CPU_AU1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case ALCHEMY_CPU_AU1550:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return platform_driver_register(&alchemy_pcictl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) arch_initcall(alchemy_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct alchemy_pci_context *ctx = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ctx && ctx->board_map_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ctx->board_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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