^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001-2003 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yoichi Yuasa <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Changes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MontaVista Software Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - New creation, NEC VR4122 and VR4131 are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline int set_pci_configuration_address(unsigned char number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Type 0 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (PCI_SLOT(devfn) < 11 || where > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) writel((1U << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (where & 0xfc), PCICONFAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Type 1 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (where > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (where & 0xfc) | 1U, PCICONFAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int size, uint32_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint32_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *val = 0xffffffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (set_pci_configuration_address(bus->number, devfn, where) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) data = readl(PCICONFDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *val = (data >> ((where & 3) << 3)) & 0xffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *val = (data >> ((where & 2) << 3)) & 0xffffU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int size, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) uint32_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (set_pci_configuration_address(bus->number, devfn, where) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) data = readl(PCICONFDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) shift = (where & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) data &= ~(0xffU << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) data |= ((val & 0xffU) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) shift = (where & 2) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) data &= ~(0xffffU << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) data |= ((val & 0xffffU) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return PCIBIOS_FUNC_NOT_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(data, PCICONFDREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_ops vr41xx_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .read = pci_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .write = pci_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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