^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on linux/arch/mips/pci/ops-tx4938.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * linux/arch/mips/pci/fixup-rbtx4938.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux/arch/mips/txx9/rbtx4938/setup.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2003-2005 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/txx9/tx4927pcic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pci_controller *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct tx4927_pcic_reg __iomem *pcicptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) } pcicptrs[2]; /* TX4938 has 2 pcic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void __init set_tx4927_pcicptr(struct pci_controller *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (pcicptrs[i].channel == channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pcicptrs[i].pcicptr = pcicptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (!pcicptrs[i].channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pcicptrs[i].channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pcicptrs[i].pcicptr = pcicptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pci_controller *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (pcicptrs[i].channel == channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return pcicptrs[i].pcicptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (bus->parent == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writel(((bus->number & 0xff) << 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | ((devfn & 0xff) << 0x08) | (where & 0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) | (bus->parent ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) &pcicptr->g2pcfgadrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* clear M_ABORT and Disable M_ABORT Int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) | (PCI_STATUS_REC_MASTER_ABORT << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) &pcicptr->pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int code = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* wait write cycle completion before checking error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (__raw_readl(&pcicptr->pcistatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) | (PCI_STATUS_REC_MASTER_ABORT << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &pcicptr->pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* flush write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) code = PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) offset ^= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) offset ^= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return __raw_readl(&pcicptr->g2pcfgdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void icd_writeb(u8 val, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) offset ^= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void icd_writew(u16 val, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) offset ^= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __raw_writel(val, &pcicptr->g2pcfgdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pci_controller *channel = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return get_tx4927_pcicptr(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (mkaddr(bus, devfn, where, pcicptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *val = icd_readb(where & 3, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *val = icd_readw(where & 3, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *val = icd_readl(pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return check_abort(pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (mkaddr(bus, devfn, where, pcicptr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) icd_writeb(val, where & 3, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) icd_writew(val, where & 3, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) icd_writel(val, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return check_abort(pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct pci_ops tx4927_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .read = tx4927_pci_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .write = tx4927_pci_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 trdyto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 retryto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 gbwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } tx4927_pci_opts = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .trdyto = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .retryto = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) char *tx4927_pcibios_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!strncmp(str, "trdyto=", 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (kstrtou8(str + 7, 0, &val) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) tx4927_pci_opts.trdyto = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!strncmp(str, "retryto=", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (kstrtou8(str + 8, 0, &val) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tx4927_pci_opts.retryto = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!strncmp(str, "gbwc=", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (kstrtou16(str + 5, 0, &val) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tx4927_pci_opts.gbwc = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct pci_controller *channel, int extarb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) set_tx4927_pcicptr(channel, pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!channel->pci_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __raw_readl(&pcicptr->pciid) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __raw_readl(&pcicptr->pciid) & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __raw_readl(&pcicptr->pciccrev) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) extarb ? "External" : "Internal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) channel->pci_ops = &tx4927_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Disable All Initiator Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __raw_writel(__raw_readl(&pcicptr->pciccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) | TX4927_PCIC_PCICCFG_G2PMEN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) | TX4927_PCIC_PCICCFG_G2PMEN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) | TX4927_PCIC_PCICCFG_G2PIOEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) &pcicptr->pciccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* GB->PCI mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __raw_writel((channel->io_resource->end - channel->io_resource->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) >> 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &pcicptr->g2piomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ____raw_writeq((channel->io_resource->start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) channel->io_map_base - IO_BASE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TX4927_PCIC_G2PIOGBASE_ECHG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TX4927_PCIC_G2PIOGBASE_BSDIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) , &pcicptr->g2piogbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ____raw_writeq(channel->io_resource->start - channel->io_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &pcicptr->g2piopbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __raw_writel(0, &pcicptr->g2pmmask[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (channel->mem_resource->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __raw_writel((channel->mem_resource->end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) - channel->mem_resource->start) >> 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &pcicptr->g2pmmask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ____raw_writeq(channel->mem_resource->start |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) TX4927_PCIC_G2PMnGBASE_ECHG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) TX4927_PCIC_G2PMnGBASE_BSDIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) , &pcicptr->g2pmgbase[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ____raw_writeq(channel->mem_resource->start -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) channel->mem_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) &pcicptr->g2pmpbase[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* PCI->GB mappings (I/O 256B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ____raw_writeq(0, &pcicptr->p2giogbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __raw_writel(0, &pcicptr->p2gm0plbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __raw_writel(0, &pcicptr->p2gm0pubase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) TX4927_PCIC_P2GMnGBASE_TECHG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) TX4927_PCIC_P2GMnGBASE_TBSDIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) , &pcicptr->p2gmgbase[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* PCI->GB mappings (MEM 16MB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* PCI->GB mappings (MEM 1MB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Clear all (including IRBER) except for GBWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __raw_writel((tx4927_pci_opts.gbwc << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) & TX4927_PCIC_PCICCFG_GBWC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) &pcicptr->pciccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Enable Initiator Memory Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (channel->mem_resource->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) __raw_writel(__raw_readl(&pcicptr->pciccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) | TX4927_PCIC_PCICCFG_G2PMEN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &pcicptr->pciccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Enable Initiator I/O Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (channel->io_resource->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __raw_writel(__raw_readl(&pcicptr->pciccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) | TX4927_PCIC_PCICCFG_G2PIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &pcicptr->pciccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Enable Initiator Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __raw_writel(__raw_readl(&pcicptr->pciccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &pcicptr->pciccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __raw_writel(0, &pcicptr->pcicfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) | (tx4927_pci_opts.trdyto & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) | ((tx4927_pci_opts.retryto & 0xff) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) &pcicptr->g2ptocnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Clear All Local Bus Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Enable All Local Bus Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Clear All Initiator Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Enable All Initiator Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Clear All PCI Status Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) | (TX4927_PCIC_PCISTATUS_ALL << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &pcicptr->pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Enable All PCI Status Error Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!extarb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Reset Bus Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __raw_writel(0, &pcicptr->pbabm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Enable Bus Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &pcicptr->pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "PCI: COMMAND=%04x,PCIMASK=%04x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __raw_readl(&pcicptr->pcistatus) & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) __raw_readl(&pcicptr->pcimask) & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __raw_readl(&pcicptr->g2ptocnt) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } pcistat_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { PCI_STATUS_PARITY, "MasterParityError" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }, g2pstat_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }, pcicstat_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { TX4927_PCIC_PCICSTATUS_PME, "PME" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int i, cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) printk(KERN_ERR "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) printk(KERN_CONT "pcistat:%04x(", pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pcistatus & pcistat_tbl[i].flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) printk(KERN_CONT "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cont++ ? " " : "", pcistat_tbl[i].str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) printk(KERN_CONT ") ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (g2pstatus & g2pstat_tbl[i].flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) printk(KERN_CONT "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cont++ ? " " : "", g2pstat_tbl[i].str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) printk(KERN_CONT ") ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (pcicstatus & pcicstat_tbl[i].flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) printk(KERN_CONT "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cont++ ? " " : "", pcicstat_tbl[i].str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) printk(KERN_CONT ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void tx4927_report_pcic_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (pcicptrs[i].pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (i % 32 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) printk(KERN_INFO "%04x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* skip registers with side-effects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) || i == offsetof(struct tx4927_pcic_reg, g2pspc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) printk(KERN_CONT " XXXXXXXX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk(KERN_CONT " %08x", __raw_readl(preg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void tx4927_dump_pcic_settings(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (pcicptrs[i].pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct pt_regs *regs = get_irq_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct tx4927_pcic_reg __iomem *pcicptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tx4927_report_pcic_status1(pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* clear all pci errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) | (TX4927_PCIC_PCISTATUS_ALL << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &pcicptr->pcistatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) console_verbose();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tx4927_dump_pcic_settings1(pcicptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) panic("PCI error.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #ifdef CONFIG_TOSHIBA_FPCIB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!pcicptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Reset Bus Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * swap reqBP and reqXP (raise priority of SLC90E66).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * PCI Backplane board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __raw_writel(0x72543610, &pcicptr->pbareqport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __raw_writel(0, &pcicptr->pbabm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Use Fixed ParkMaster (required by SLC90E66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Enable Bus Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) TX4927_PCIC_PBACFG_PBAEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &pcicptr->pbacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __raw_readl(&pcicptr->pbareqport));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tx4927_quirk_slc90e66_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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