Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright 2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *              ahennessy@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *     Define the pci_ops for TX3927.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Much of the code is derived from the original DDB5074 port by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Geert Uytterhoeven <geert@linux-m68k.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  This program is free software; you can redistribute  it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  under  the terms of  the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  Free Software Foundation;  either version 2 of the  License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/txx9irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/txx9/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <asm/txx9/tx3927.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (bus->parent == NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	    devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	tx3927_pcicptr->ica =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		((bus->number & 0xff) << 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		((devfn & 0xff) << 0x08) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		(where & 0xfc) | (bus->parent ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* clear M_ABORT and Disable M_ABORT Int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline int check_abort(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		/* flush write buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (mkaddr(bus, devfn, where)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		*val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		*val = le32_to_cpu(tx3927_pcicptr->icd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return check_abort();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (mkaddr(bus, devfn, where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	    cpu_to_le16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		tx3927_pcicptr->icd = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return check_abort();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct pci_ops tx3927_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.read = tx3927_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.write = tx3927_pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __init tx3927_pcic_setup(struct pci_controller *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			      unsigned long sdram_size, int extarb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned long io_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		channel->io_resource->start + mips_io_port_base - IO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned long io_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		channel->io_resource->end - channel->io_resource->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned long io_pciaddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		channel->io_resource->start - channel->io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long mem_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		channel->mem_resource->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned long mem_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		channel->mem_resource->end - channel->mem_resource->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned long mem_pciaddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		channel->mem_resource->start - channel->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	       tx3927_pcicptr->did, tx3927_pcicptr->vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	       tx3927_pcicptr->rid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	       extarb ? "External" : "Internal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	channel->pci_ops = &tx3927_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Disable External PCI Config. Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		TX3927_PCIC_LBC_TIBSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* LB->PCI mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tx3927_pcicptr->iomas = ~(io_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	tx3927_pcicptr->ilbioma = io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	tx3927_pcicptr->ipbioma = io_pciaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	tx3927_pcicptr->mmas = ~(mem_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	tx3927_pcicptr->ilbmma = mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tx3927_pcicptr->ipbmma = mem_pciaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* PCI->LB mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	tx3927_pcicptr->iobas = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tx3927_pcicptr->ioba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	tx3927_pcicptr->tlbioma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	tx3927_pcicptr->mbas = ~(sdram_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	tx3927_pcicptr->mba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	tx3927_pcicptr->tlbmma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Enable Direct mapping Address Space Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* Clear All Local Bus Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Enable All Local Bus Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* Clear All PCI Status Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Enable All PCI Status Error Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* PCIC Int => IRC IRQ10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tx3927_pcicptr->il = TX3927_IR_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* Target Control (per errata) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Enable Bus Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (!extarb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct pt_regs *regs = get_irq_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		       regs->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		       tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		/* clear all pci errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	console_verbose();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	panic("PCI error.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __init tx3927_setup_pcierr_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			tx3927_pcierr_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			0, "PCI error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			(void *)TX3927_PCIC_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		printk(KERN_WARNING "Failed to request irq for PCIERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }