^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * SNI specific PCI support for RM200/RM300.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1997 - 2000, 2003 Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/sni.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * address are decoded. We therefore manually have to reject attempts at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * reading outside this range. Being on the paranoid side we only do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * test for bus 0 and hope forwarding and decoding work properly for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * subordinated busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ASIC PCI only supports type 1 config cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if ((devfn > 255) || (reg > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (busno == 0 && devfn >= PCI_DEVFN(8, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *(volatile u32 *)PCIMT_CONFIG_ADDRESS =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((busno & 0xff) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ((devfn & 0xff) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (reg & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if ((res = set_config_address(bus->number, devfn, reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *val = inl(PCIMT_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if ((res = set_config_address(bus->number, devfn, reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) outb(val, PCIMT_CONFIG_DATA + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) outw(val, PCIMT_CONFIG_DATA + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) outl(val, PCIMT_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pci_ops sni_pcimt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .read = pcimt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .write = pcimt_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if ((devfn > 255) || (reg > 255) || (busno > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * on bus 0 we need to check, whether there is a device answering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * for the devfn by doing a config write and checking the result. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * we don't do it, we will get a data bus error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pcit_set_config_address(0, 0, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) outl(inl(0xcfc) | 0xc0000000, 0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((res = pcit_set_config_address(0, devfn, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) outl(0xffffffff, 0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pcit_set_config_address(0, 0, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (inl(0xcfc) & 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if ((res = pcit_set_config_address(bus->number, devfn, reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *val = inl(PCIMT_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if ((res = pcit_set_config_address(bus->number, devfn, reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outb(val, PCIMT_CONFIG_DATA + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outw(val, PCIMT_CONFIG_DATA + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) outl(val, PCIMT_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pci_ops sni_pcit_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .read = pcit_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .write = pcit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags