^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Carsten Langgaard <carstenl@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MIPS boards specific PCI support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mips-boards/msc01_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCI_ACCESS_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_ACCESS_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * PCI configuration cycle AD bus definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_CFG_TYPE0_REG_SHF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_CFG_TYPE0_FUNC_SHF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_CFG_TYPE1_REG_SHF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_CFG_TYPE1_FUNC_SHF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_CFG_TYPE1_DEV_SHF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_CFG_TYPE1_BUS_SHF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int msc_pcibios_config_access(unsigned char access_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned char busnum = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Clear status register bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MSC_WRITE(MSC01_PCI_INTSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MSC_WRITE(MSC01_PCI_CFGADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Perform access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (access_type == PCI_ACCESS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MSC_WRITE(MSC01_PCI_CFGDATA, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MSC_READ(MSC01_PCI_CFGDATA, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Detect Master/Target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MSC_READ(MSC01_PCI_INTSTAT, intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MSC_WRITE(MSC01_PCI_INTSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * We can't address 8 and 16 bit words directly. Instead we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * read/write a 32bit word and mask/modify the data we actually want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pci_ops msc_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .read = msc_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .write = msc_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags