^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Carsten Langgaard <carstenl@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Lemote Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Wu Zhangjin <wuzhangjin@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <loongson.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifdef CONFIG_CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <cs5536/cs5536_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <cs5536/cs5536.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_ACCESS_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_ACCESS_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CFG_SPACE_REG(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ID_SEL_BEGIN 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int loongson_pcibios_config_access(unsigned char access_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 busnum = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 addr, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void *addrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int device = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int function = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (busnum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* board-specific part,currently,only fuloong2f,yeeloong2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * use CS5536, fuloong2e use via686b, gdium has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * south bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * will not go this branch, but the others. so, no calling dead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * loop here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) switch (access_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case PCI_ACCESS_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *data = cs5536_pci_conf_read4(function, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case PCI_ACCESS_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cs5536_pci_conf_write4(function, reg, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Type 0 configuration for onboard PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (device > MAX_DEV_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Type 1 configuration for offboard PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) type = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Clear aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) LOONGSON_PCICMD_MTABORT_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Flush Bonito register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dummy = LOONGSON_PCIMAP_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) addrp = CFG_SPACE_REG(addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (access_type == PCI_ACCESS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(cpu_to_le32(*data), addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *data = le32_to_cpu(readl(addrp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Detect Master/Target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LOONGSON_PCICMD_MTABORT_CLR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LOONGSON_PCICMD_MTABORT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * We can't address 8 and 16 bit words directly. Instead we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * read/write a 32bit word and mask/modify the data we actually want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct pci_ops loongson_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .read = loongson_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .write = loongson_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef CONFIG_CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_RAW_SPINLOCK(msr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void _rdmsr(u32 msr, u32 *hi, u32 *lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pci_bus bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .number = PCI_BUS_CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) raw_spin_lock_irqsave(&msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) raw_spin_unlock_irqrestore(&msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) EXPORT_SYMBOL(_rdmsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void _wrmsr(u32 msr, u32 hi, u32 lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct pci_bus bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .number = PCI_BUS_CS5536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) raw_spin_lock_irqsave(&msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) raw_spin_unlock_irqrestore(&msr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EXPORT_SYMBOL(_wrmsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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