^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Carsten Langgaard <carstenl@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/gt64120.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCI_ACCESS_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCI_ACCESS_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * PCI configuration cycle AD bus definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_CFG_TYPE0_REG_SHF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_CFG_TYPE0_FUNC_SHF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_CFG_TYPE1_REG_SHF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_CFG_TYPE1_FUNC_SHF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_CFG_TYPE1_DEV_SHF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_CFG_TYPE1_BUS_SHF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char busnum = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return -1; /* Because of a bug in the galileo (for slot 31). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Clear cause register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GT_INTRCAUSE_TARABORT0_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Setup address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GT_WRITE(GT_PCI0_CFGADDR_OFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GT_PCI0_CFGADDR_CONFIGEN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (access_type == PCI_ACCESS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (busnum == 0 && PCI_SLOT(devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The Galileo system controller is acting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * differently than other devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (busnum == 0 && PCI_SLOT(devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * The Galileo system controller is acting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * differently than other devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *data = GT_READ(GT_PCI0_CFGDATA_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *data = __GT_READ(GT_PCI0_CFGDATA_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Check for master or target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) intr = GT_READ(GT_INTRCAUSE_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GT_INTRCAUSE_TARABORT0_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * We can't address 8 and 16 bit words directly. Instead we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * read/write a 32bit word and mask/modify the data we actually want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) devfn, where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pci_ops gt64xxx_pci0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .read = gt64xxx_pci0_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .write = gt64xxx_pci0_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags