^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Carsten Langgaard <carstenl@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * MIPS boards specific PCI support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mips-boards/bonito64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_ACCESS_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCI_ACCESS_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ID_SEL_BEGIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int bonito64_pcibios_config_access(unsigned char access_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 busnum = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 addr, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void *addrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int device = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int function = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (busnum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Type 0 configuration for onboard PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (device > MAX_DEV_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Type 1 configuration for offboard PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) type = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Clear aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) BONITO_PCIMAP_CFG = (addr >> 16) | type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Flush Bonito register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dummy = BONITO_PCIMAP_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) addrp = CFG_SPACE_REG(addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (access_type == PCI_ACCESS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel(cpu_to_le32(*data), addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Wait till done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) while (BONITO_PCIMSTAT & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *data = le32_to_cpu(readl(addrp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Detect Master/Target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) BONITO_PCICMD_MTABORT_CLR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BONITO_PCICMD_MTABORT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * We can't address 8 and 16 bit words directly. Instead we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * read/write a 32bit word and mask/modify the data we actually want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int bonito64_pcibios_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int where, int size, u32 * val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *val = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *val = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int bonito64_pcibios_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if ((size == 2) && (where & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) else if ((size == 4) && (where & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) where, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data = (data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data = (data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (bonito64_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pci_ops bonito64_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .read = bonito64_pcibios_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .write = bonito64_pcibios_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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