^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pci-bcm63xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * swizzle 32bits data to return only the needed part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int postprocess_read(u32 data, int where, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ret = (data >> ((where & 3) << 3)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ret = (data >> ((where & 3) << 3)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ret = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int preprocess_write(u32 orig_data, u32 val, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (val << ((where & 3) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * setup hardware for a configuration cycle with given parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int slot, func, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) func = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = where >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ok, setup config access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = (reg << MPI_L2PCFG_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val |= (func << MPI_L2PCFG_FUNC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val |= MPI_L2PCFG_CFG_USEREG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val |= MPI_L2PCFG_CFG_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* type 0 cycle for local bus, type 1 cycle for anything else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (type != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* FIXME: how to specify bus ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bcm_mpi_writel(val, MPI_L2PCFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int bcm63xx_do_cfg_read(int type, unsigned int busn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int devfn, int where, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* two phase cycle, first we write address, then read data at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * another location, caller already has a spinlock so no need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * to add one here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data = le32_to_cpu(__raw_readl(pci_iospace_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* restore IO space normal behaviour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bcm_mpi_writel(0, MPI_L2PCFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *val = postprocess_read(data, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int bcm63xx_do_cfg_write(int type, unsigned int busn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int devfn, int where, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* two phase cycle, first we write address, then write data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * another location, caller already has a spinlock so no need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * to add one here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data = le32_to_cpu(__raw_readl(pci_iospace_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data = preprocess_write(data, val, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __raw_writel(cpu_to_le32(data), pci_iospace_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* no way to know the access is done, we have to wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* restore IO space normal behaviour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bcm_mpi_writel(0, MPI_L2PCFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) type = bus->parent ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return bcm63xx_do_cfg_read(type, bus->number, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) type = bus->parent ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return bcm63xx_do_cfg_write(type, bus->number, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct pci_ops bcm63xx_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .read = bcm63xx_pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .write = bcm63xx_pci_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_CARDBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * emulate configuration read access on a cardbus bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FAKE_CB_BRIDGE_SLOT 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int fake_cb_bridge_bus_number = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 pci_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 cb_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 subordinate_busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 cardbus_busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 pci_busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int bus_assigned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u16 bridge_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 mem_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 mem_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 mem_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 io_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 io_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 io_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 io_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } fake_cb_bridge_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int fake_cb_bridge_read(int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = where >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case (PCI_VENDOR_ID >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* create dummy vendor/device id from our cpu id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case (PCI_COMMAND >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data = (PCI_STATUS_DEVSEL_SLOW << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) data |= fake_cb_bridge_regs.pci_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case (PCI_CLASS_REVISION >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case (PCI_CACHE_LINE_SIZE >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) data = (PCI_HEADER_TYPE_CARDBUS << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case (PCI_INTERRUPT_LINE >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* bridge control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) data = (fake_cb_bridge_regs.bridge_control << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* pin:intA line:0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) data |= (0x1 << 8) | 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case (PCI_CB_PRIMARY_BUS >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) data = (fake_cb_bridge_regs.cb_latency << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) data |= (fake_cb_bridge_regs.subordinate_busn << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data |= (fake_cb_bridge_regs.cardbus_busn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) data |= fake_cb_bridge_regs.pci_busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case (PCI_CB_MEMORY_BASE_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) data = fake_cb_bridge_regs.mem_base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case (PCI_CB_MEMORY_LIMIT_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) data = fake_cb_bridge_regs.mem_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case (PCI_CB_MEMORY_BASE_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) data = fake_cb_bridge_regs.mem_base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case (PCI_CB_MEMORY_LIMIT_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) data = fake_cb_bridge_regs.mem_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case (PCI_CB_IO_BASE_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* | 1 for 32bits io support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data = fake_cb_bridge_regs.io_base0 | 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case (PCI_CB_IO_LIMIT_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) data = fake_cb_bridge_regs.io_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case (PCI_CB_IO_BASE_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* | 1 for 32bits io support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) data = fake_cb_bridge_regs.io_base1 | 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case (PCI_CB_IO_LIMIT_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) data = fake_cb_bridge_regs.io_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *val = postprocess_read(data, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * emulate configuration write access on a cardbus bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int fake_cb_bridge_write(int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 data, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data = preprocess_write(data, val, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = where >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case (PCI_COMMAND >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fake_cb_bridge_regs.pci_command = (data & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case (PCI_CB_PRIMARY_BUS >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) fake_cb_bridge_regs.pci_busn = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (fake_cb_bridge_regs.cardbus_busn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fake_cb_bridge_regs.bus_assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case (PCI_INTERRUPT_LINE >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tmp = (data >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* disable memory prefetch support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fake_cb_bridge_regs.bridge_control = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case (PCI_CB_MEMORY_BASE_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fake_cb_bridge_regs.mem_base0 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case (PCI_CB_MEMORY_LIMIT_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) fake_cb_bridge_regs.mem_limit0 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case (PCI_CB_MEMORY_BASE_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fake_cb_bridge_regs.mem_base1 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case (PCI_CB_MEMORY_LIMIT_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) fake_cb_bridge_regs.mem_limit1 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case (PCI_CB_IO_BASE_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fake_cb_bridge_regs.io_base0 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case (PCI_CB_IO_LIMIT_0 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fake_cb_bridge_regs.io_limit0 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case (PCI_CB_IO_BASE_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fake_cb_bridge_regs.io_base1 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case (PCI_CB_IO_LIMIT_1 >> 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fake_cb_bridge_regs.io_limit1 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* snoop access to slot 0x1e on root bus, we fake a cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * bridge at this location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) fake_cb_bridge_bus_number = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return fake_cb_bridge_read(where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* a configuration cycle for the device behind the cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * bridge is actually done as a type 0 cycle on the primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * bus. This means that only one device can be on the cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (fake_cb_bridge_regs.bus_assigned &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bus->number == fake_cb_bridge_regs.cardbus_busn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PCI_SLOT(devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return bcm63xx_do_cfg_read(0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) fake_cb_bridge_bus_number = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return fake_cb_bridge_write(where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (fake_cb_bridge_regs.bus_assigned &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bus->number == fake_cb_bridge_regs.cardbus_busn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PCI_SLOT(devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return bcm63xx_do_cfg_write(0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct pci_ops bcm63xx_cb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .read = bcm63xx_cb_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .write = bcm63xx_cb_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * only one IO window, so it cannot be shared by PCI and cardbus, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * fixup to choose and detect unhandled configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void bcm63xx_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int io_window = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i, found, new_io_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* look for any io resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* skip our fake bus with only cardbus bridge on it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (dev->bus->number == fake_cb_bridge_bus_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* find on which bus the device is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (fake_cb_bridge_regs.bus_assigned &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PCI_SLOT(dev->devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) new_io_window = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) new_io_window = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (new_io_window == io_window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (io_window != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "need IO, which hardware cannot do\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) (new_io_window == 0) ? "PCI" : "cardbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (io_window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) io_window = new_io_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) switch (bus->number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case PCIE_BUS_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return PCI_SLOT(devfn) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case PCIE_BUS_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (PCI_SLOT(devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return bcm_pcie_readl(PCIE_DLSTATUS_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) & DLSTATUS_PHYLINKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!bcm63xx_pcie_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (bus->number == PCIE_BUS_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) reg += PCIE_DEVICE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) data = bcm_pcie_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *val = postprocess_read(data, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!bcm63xx_pcie_can_access(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (bus->number == PCIE_BUS_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) reg += PCIE_DEVICE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) data = bcm_pcie_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) data = preprocess_write(data, val, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bcm_pcie_writel(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct pci_ops bcm63xx_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .read = bcm63xx_pcie_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .write = bcm63xx_pcie_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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