^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2003-2012 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/netlogic/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/netlogic/mips-extns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/netlogic/xlp-hal/pic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/netlogic/xlp-hal/pcibus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/netlogic/xlp-hal/bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XLP_MSIVEC_PER_LINK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XLP_MSIXVEC_TOTAL (cpu_is_xlp9xx() ? 128 : 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XLP_MSIXVEC_PER_LINK (cpu_is_xlp9xx() ? 32 : 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline int nlm_link_msiirq(int link, int msivec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* get the link MSI vector from irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline int nlm_irq_msivec(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return (irq - NLM_MSI_VEC_BASE) % XLP_MSIVEC_PER_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* get the link from the irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline int nlm_irq_msilink(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int total_msivec = XLP_MSIVEC_PER_LINK * PCIE_NLINKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ((irq - NLM_MSI_VEC_BASE) % total_msivec) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) XLP_MSIVEC_PER_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * For XLP 8xx/4xx/3xx/2xx, only 32 MSI-X vectors are possible because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * there are only 32 PIC interrupts for MSI. We split them statically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * and use 8 MSI-X vectors per link - this keeps the allocation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * lookup simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * On XLP 9xx, there are 32 vectors per link, and the interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * not routed thru PIC, so we can use all 128 MSI-X vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline int nlm_link_msixirq(int link, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* get the link MSI vector from irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int nlm_irq_msixvec(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return (irq - NLM_MSIX_VEC_BASE) % XLP_MSIXVEC_TOTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* get the link from MSIX vec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline int nlm_irq_msixlink(int msixvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return msixvec / XLP_MSIXVEC_PER_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Per link MSI and MSI-X information, set as IRQ handler data for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * MSI and MSI-X interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct xlp_msi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct nlm_soc_info *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) uint64_t lnkbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint32_t msi_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint32_t msi_alloc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint32_t msix_alloc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spinlock_t msi_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * MSI Chip definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * On XLP, there is a PIC interrupt associated with each PCIe link on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * per link and 128 overall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * When a device connected to the link raises a MSI interrupt, we get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * link interrupt and we then have to look at PCIE_MSI_STATUS register at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * the bridge to map it to the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void xlp_msi_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) vec = nlm_irq_msivec(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock_irqsave(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) md->msi_enabled_mask |= 1u << vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) md->msi_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void xlp_msi_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) vec = nlm_irq_msivec(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_lock_irqsave(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) md->msi_enabled_mask &= ~(1u << vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) md->msi_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void xlp_msi_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int link, vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) link = nlm_irq_msilink(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) vec = nlm_irq_msivec(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xlp_msi_disable(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Ack MSI on bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct irq_chip xlp_msi_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "XLP-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .irq_enable = xlp_msi_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .irq_disable = xlp_msi_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .irq_mask_ack = xlp_msi_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .irq_unmask = xlp_msi_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * XLP8XX/4XX/3XX/2XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * The MSI-X interrupt handling is different from MSI, there are 32 MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * interrupts generated by the PIC and each of these correspond to a MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * vector (0-31) that can be assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * We divide the MSI-X vectors to 8 per link and do a per-link allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * XLP9XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 32 MSI-X vectors are available per link, and the interrupts are not routed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * thru the PIC. PIC ack not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Enable and disable done using standard MSI functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void xlp_msix_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int link, msixvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uint32_t status_reg, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) msixvec = nlm_irq_msixvec(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) link = nlm_irq_msixlink(msixvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) md = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Ack MSI on bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) status_reg = PCIE_9XX_MSIX_STATUSX(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bit = msixvec % XLP_MSIXVEC_PER_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) status_reg = PCIE_MSIX_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bit = msixvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) nlm_pic_ack(md->node->picbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PIC_IRT_PCIE_MSIX_INDEX(msixvec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct irq_chip xlp_msix_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "XLP-MSIX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .irq_enable = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .irq_disable = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .irq_mask_ack = xlp_msix_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void arch_teardown_msi_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Setup a PCIe link for MSI. By default, the links are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * legacy interrupt mode. We will switch them to MSI mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * at the first MSI request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if ((val & 0x200) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= 0x200; /* MSI Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if ((val & 0x200) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val = nlm_read_reg(lnkbase, 0x1); /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if ((val & 0x0400) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val |= 0x0400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) nlm_write_reg(lnkbase, 0x1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Update IRQ in the PCI irq reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val = nlm_read_pci_reg(lnkbase, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val &= ~0x1fu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val |= (1 << 8) | lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) nlm_write_pci_reg(lnkbase, 0xf, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* MSI addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* MSI cap for bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if ((val & (1 << 16)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val |= 0xb << 16; /* mmc32, msi enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Allocate a MSI vector on a link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int msivec, irt, lirq, xirq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint64_t msiaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Get MSI data for the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lirq = PIC_PCIE_LINK_MSI_IRQ(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) md = irq_get_chip_data(xirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) msiaddr = MSI_LINK_ADDR(node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (md->msi_alloc_mask == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) xlp_config_link_msi(lnkbase, lirq, msiaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* switch the link IRQ to MSI range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) irt = PIC_9XX_IRT_PCIE_LINK_INDEX(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) irt = PIC_IRT_PCIE_LINK_INDEX(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) nlm_setup_pic_irq(node, lirq, lirq, irt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) node * nlm_threads_per_node(), 1 /*en */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* allocate a MSI vec, and tell the bridge about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msivec = fls(md->msi_alloc_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (msivec == XLP_MSIVEC_PER_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) md->msi_alloc_mask |= (1u << msivec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) msg.address_hi = msiaddr >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) msg.address_lo = msiaddr & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) msg.data = 0xc00 | msivec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) xirq = xirq + msivec; /* msi mapped to global irq space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = irq_set_msi_desc(xirq, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pci_write_msi_msg(xirq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Switch a link to MSI-X mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val = nlm_read_reg(lnkbase, 0x2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if ((val & 0x80000000U) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= 0x80000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) nlm_write_reg(lnkbase, 0x2C, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if ((val & 0x200) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val |= 0x200; /* MSI Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if ((val & 0x200) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val |= 0x200; /* MSI Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val = nlm_read_reg(lnkbase, 0x1); /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if ((val & 0x0400) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val |= 0x0400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nlm_write_reg(lnkbase, 0x1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Update IRQ in the PCI irq reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = nlm_read_pci_reg(lnkbase, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val &= ~0x1fu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val |= (1 << 8) | lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) nlm_write_pci_reg(lnkbase, 0xf, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* MSI-X addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) msixaddr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (msixaddr + MSI_ADDR_SZ) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* MSI-X addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) msixaddr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (msixaddr + MSI_ADDR_SZ) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Allocate a MSI-X vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int t, msixvec, lirq, xirq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) uint64_t msixaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Get MSI data for the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) lirq = PIC_PCIE_MSIX_IRQ(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) md = irq_get_chip_data(xirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msixaddr = MSIX_LINK_ADDR(node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spin_lock_irqsave(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* switch the PCIe link to MSI-X mode at the first alloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (md->msix_alloc_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) xlp_config_link_msix(lnkbase, lirq, msixaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* allocate a MSI-X vec, and tell the bridge about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) t = fls(md->msix_alloc_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (t == XLP_MSIXVEC_PER_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) md->msix_alloc_mask |= (1u << t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spin_unlock_irqrestore(&md->msi_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) xirq += t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msixvec = nlm_irq_msixvec(xirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msg.address_hi = msixaddr >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msg.address_lo = msixaddr & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msg.data = 0xc00 | msixvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = irq_set_msi_desc(xirq, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_write_msi_msg(xirq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct pci_dev *lnkdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uint64_t lnkbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int node, link, slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) lnkdev = xlp_get_pcie_link(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (lnkdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&dev->dev, "Could not find bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) slot = PCI_SLOT(lnkdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) link = PCI_FUNC(lnkdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) node = slot / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) lnkbase = nlm_get_pcie_base(node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (desc->msi_attrib.is_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return xlp_setup_msix(lnkbase, node, link, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return xlp_setup_msi(lnkbase, node, link, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void __init xlp_init_node_msi_irqs(int node, int link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct nlm_soc_info *nodep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int irq, i, irt, msixvec, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pr_info("[%d %d] Init node PCI IRT\n", node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) nodep = nlm_get_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Alloc an MSI block for the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) md = kzalloc(sizeof(*md), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_lock_init(&md->msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) md->msi_enabled_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) md->msi_alloc_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) md->msix_alloc_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) md->node = nodep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) md->lnkbase = nlm_get_pcie_base(node, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* extended space for MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) irq_set_chip_data(i, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val = ((node * nlm_threads_per_node()) << 7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PIC_PCIE_MSIX_IRQ(link) << 1 | 0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (link * XLP_MSIXVEC_PER_LINK)), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Initialize MSI-X irts to generate one interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * per link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msixvec = link * XLP_MSIXVEC_PER_LINK + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) nlm_pic_init_irt(nodep->picbase, irt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PIC_PCIE_MSIX_IRQ(link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) node * nlm_threads_per_node(), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Initialize MSI-X extended irq space for the link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) irq_set_chip_data(irq, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void nlm_dispatch_msi(int node, int lirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int link, i, irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) md = irq_get_chip_data(irqbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) md->msi_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) md->msi_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) i = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) do_IRQ(irqbase + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) status &= status - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Ack at eirr and PIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) nlm_pic_ack(md->node->picbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PIC_9XX_IRT_PCIE_LINK_INDEX(link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void nlm_dispatch_msix(int node, int lirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct xlp_msi_data *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int link, i, irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) md = irq_get_chip_data(irqbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* narrow it down to the MSI-x vectors for our link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) status = (status >> (link * XLP_MSIXVEC_PER_LINK)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ((1 << XLP_MSIXVEC_PER_LINK) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) i = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) do_IRQ(irqbase + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) status &= status - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Ack at eirr and PIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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