Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2005	Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/vr41xx/tb0287.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	unsigned char bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	int irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	bus = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	if (bus == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			irq = TB0287_SM501_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		case 17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			irq = TB0287_SIL680A_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	} else if (bus == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		switch (PCI_SLOT(dev->devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			irq = TB0287_PCI_SLOT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			irq = TB0287_RTL8110_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	} else if (bus > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		irq = TB0287_PCI_SLOT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }