Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2002-2005  Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/vr41xx/giu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/vr41xx/tb0226.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	int irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		vr41xx_set_irq_trigger(GD82559_1_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 				       IRQ_TRIGGER_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				       IRQ_SIGNAL_THROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		irq = GD82559_1_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		vr41xx_set_irq_trigger(GD82559_2_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 				       IRQ_TRIGGER_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 				       IRQ_SIGNAL_THROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		irq = GD82559_2_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 					       IRQ_TRIGGER_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 					       IRQ_SIGNAL_THROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			vr41xx_set_irq_level(UPD720100_INTA_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 					     IRQ_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			irq = UPD720100_INTA_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 					       IRQ_TRIGGER_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 					       IRQ_SIGNAL_THROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			vr41xx_set_irq_level(UPD720100_INTB_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 					     IRQ_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			irq = UPD720100_INTB_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 					       IRQ_TRIGGER_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 					       IRQ_SIGNAL_THROUGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			vr41xx_set_irq_level(UPD720100_INTC_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 					     IRQ_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			irq = UPD720100_INTC_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }