^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * SNI specific PCI support for RM200/RM300.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1997 - 2000, 2003, 04 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/sni.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * PCIMT Shortcuts ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCSI PCIMT_IRQ_SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ETH PCIMT_IRQ_ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTA PCIMT_IRQ_INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define INTB PCIMT_IRQ_INTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTC PCIMT_IRQ_INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTD PCIMT_IRQ_INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Device 0: PCI EISA Bridge (directly routed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Device 1: NCR53c810 SCSI (directly routed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Device 2: PCnet32 Ethernet (directly routed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Device 3: VGA (routed to INTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Device 4: Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Device 5: Slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Device 6: Slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Device 7: Slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Documentation says the VGA is device 5 and device 3 is unused but that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * seem to be a documentation error. At least on my RM200C the Cirrus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Logic CL-GD5434 VGA is device 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static char irq_tab_rm200[8][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0, 0, 0, 0, 0 }, /* EISA bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { INTB, INTB, INTB, INTB, INTB }, /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * In Revision D of the RM300 Device 2 has become a normal purpose Slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The VGA card is optional for RM300 systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static char irq_tab_rm300d[8][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0, 0, 0, 0, 0 }, /* EISA bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { INTB, INTB, INTB, INTB, INTB }, /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static char irq_tab_rm300e[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0, 0, 0, 0, 0 }, /* HOST bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0, INTA, INTB, INTC, INTD }, /* Slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #undef SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #undef ETH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #undef INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #undef INTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #undef INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #undef INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * PCIT Shortcuts ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SCSI0 PCIT_IRQ_SCSI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCSI1 PCIT_IRQ_SCSI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ETH PCIT_IRQ_ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define INTA PCIT_IRQ_INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define INTB PCIT_IRQ_INTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INTC PCIT_IRQ_INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTD PCIT_IRQ_INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static char irq_tab_pcit[13][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0, 0, 0, 0, 0 }, /* HOST bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0, INTA, INTB, INTC, INTD }, /* Slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static char irq_tab_pcit_cplus[13][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0, 0, 0, 0, 0 }, /* HOST bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0, 0, 0, 0, 0 }, /* PCI-EISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0, 0, 0, 0, 0 }, /* Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0, INTB, INTC, INTD, INTA }, /* fixup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline int is_rm300_revd(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned char csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return (csmsr & 0xa0) == 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) switch (sni_brd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case SNI_BRD_PCI_TOWER_CPLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (slot == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * SNI messed up interrupt wiring for onboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * PCI bus 1; we need to fix this up here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) while (dev && dev->bus->number != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (dev && dev->devfn >= PCI_DEVFN(4, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return irq_tab_pcit_cplus[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case SNI_BRD_PCI_TOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return irq_tab_pcit[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case SNI_BRD_PCI_MTOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (is_rm300_revd())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return irq_tab_rm300d[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case SNI_BRD_PCI_DESKTOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return irq_tab_rm200[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case SNI_BRD_PCI_MTOWER_CPLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return irq_tab_rm300e[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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