^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Maciej W. Rozycki <macro@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Set the BCM1250, etc. PCI host bridge's TRDY timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * to the finite max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static void quirk_sb1250_pci(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) pci_write_config_byte(dev, 0x40, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) quirk_sb1250_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The BCM1250, etc. PCI host bridge does not support DAC on its 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * bus, so we set the bus's DMA limit accordingly. However the HT link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * down the artificial PCI-HT bridge supports 40-bit addressing and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * SP1011 HT-PCI bridge downstream supports both DAC and a 64-bit bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * width, so we record the PCI-HT bridge's secondary and subordinate bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * numbers and do not set the limit for devices present in the inclusive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * range of those.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct sb1250_bus_dma_limit_exclude {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned char end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int sb1250_bus_dma_limit(struct pci_dev *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sb1250_bus_dma_limit_exclude *exclude = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool exclude_this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool ht_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) exclude_this = exclude->set && (dev->bus->number >= exclude->start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dev->bus->number <= exclude->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ht_bridge = !exclude->set && (dev->vendor == PCI_VENDOR_ID_SIBYTE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev->device == PCI_DEVICE_ID_BCM1250_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (exclude_this) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_dbg(&dev->dev, "not disabling DAC for device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } else if (ht_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) exclude->start = dev->subordinate->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) exclude->end = pci_bus_max_busnr(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) exclude->set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_dbg(&dev->dev, "not disabling DAC for [bus %02x-%02x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) exclude->start, exclude->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_dbg(&dev->dev, "disabling DAC for device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev->dev.bus_dma_limit = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void quirk_sb1250_pci_dac(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct sb1250_bus_dma_limit_exclude exclude = { .set = false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pci_walk_bus(dev->bus, sb1250_bus_dma_limit, &exclude);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) quirk_sb1250_pci_dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void quirk_sb1250_ht(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev->class = PCI_CLASS_BRIDGE_PCI << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) quirk_sb1250_ht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void quirk_sp1011(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_write_config_byte(dev, 0x64, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIPACKETS, PCI_DEVICE_ID_SP1011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) quirk_sp1011);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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