Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <asm/mips-boards/piix4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /* PCI interrupt pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define PCIA		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define PCIB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define PCIC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define PCID		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* This table is filled in by interrogating the PIIX4 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static char pci_irq[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static char irq_tab[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	/*	INTA	INTB	INTC	INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	{0,	0,	0,	0,	0 },	/*  0: GT64120 PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	{0,	0,	0,	0,	0 },	/*  1: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	{0,	0,	0,	0,	0 },	/*  2: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	{0,	0,	0,	0,	0 },	/*  3: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	{0,	0,	0,	0,	0 },	/*  4: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{0,	0,	0,	0,	0 },	/*  5: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{0,	0,	0,	0,	0 },	/*  6: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{0,	0,	0,	0,	0 },	/*  7: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{0,	0,	0,	0,	0 },	/*  8: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{0,	0,	0,	0,	0 },	/*  9: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{0,	0,	0,	0,	PCID }, /* 10: PIIX4 USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{0,	PCIB,	0,	0,	0 },	/* 11: AMD 79C973 Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{0,	PCIC,	0,	0,	0 },	/* 12: Crystal 4281 Sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{0,	0,	0,	0,	0 },	/* 13: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{0,	0,	0,	0,	0 },	/* 14: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{0,	0,	0,	0,	0 },	/* 15: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{0,	0,	0,	0,	0 },	/* 16: Unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{0,	0,	0,	0,	0 },	/* 17: Bonito/SOC-it PCI Bridge*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	{0,	PCIA,	PCIB,	PCIC,	PCID }, /* 18: PCI Slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{0,	PCIB,	PCIC,	PCID,	PCIA }, /* 19: PCI Slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{0,	PCIC,	PCID,	PCIA,	PCIB }, /* 20: PCI Slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{0,	PCID,	PCIA,	PCIB,	PCIC }	/* 21: PCI Slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	virq = irq_tab[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return pci_irq[virq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void malta_piix_func3_base_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* Set a sane PM I/O base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Enable access to the PM I/O region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			      PIIX4_FUNC3_PMREGMISC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			malta_piix_func3_base_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void malta_piix_func0_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 reg_val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u16 reg_val16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* PIIX PIRQC[A:D] irq mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		0,  0,	0,  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		4,  5,	6,  7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		0,  9, 10, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		12, 0, 14, 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Interrogate PIIX4 to get PCI IRQ mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	for (i = 0; i <= 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			pci_irq[PCIA+i] = 0;	/* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			pci_irq[PCIA+i] = piixirqmap[reg_val &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Done by YAMON 2.00 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (PCI_SLOT(pdev->devfn) == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * Set top of main memory accessible by ISA or DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * devices to 16 Mb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Mux SERIRQ to its pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			       reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Enable SERIRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Enable response to special cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	pci_write_config_word(pdev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			      reg_val16 | PCI_COMMAND_SPECIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 malta_piix_func0_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void malta_piix_func1_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Done by YAMON 2.02 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (PCI_SLOT(pdev->devfn) == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		 * IDE Decode enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			&reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			&reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 malta_piix_func1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Enable PCI 2.1 compatibility in PIIX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void quirk_dlcsetup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u8 odlc, ndlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	(void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Enable passive releases and delayed transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		      PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		      PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	(void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	quirk_dlcsetup);