Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <asm/ip32/ip32_ints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * O2 has up to 5 PCI devices connected into the MACE bridge.  The device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * map looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * 0  aic7xxx 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * 1  aic7xxx 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * 2  expansion slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * 3  N/C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * 4  N/C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SCSI0  MACEPCI_SCSI0_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCSI1  MACEPCI_SCSI1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define INTA0  MACEPCI_SLOT0_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INTA1  MACEPCI_SLOT1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INTA2  MACEPCI_SLOT2_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define INTB   MACEPCI_SHARED0_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTC   MACEPCI_SHARED1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTD   MACEPCI_SHARED2_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static char irq_tab_mace[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)       /* Dummy	INT#A  INT#B  INT#C  INT#D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{0,	    0,	   0,	  0,	 0}, /* This is placeholder row - never used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{0,	SCSI0, SCSI0, SCSI0, SCSI0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{0,	SCSI1, SCSI1, SCSI1, SCSI1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	{0,	INTA0,	INTB,  INTC,  INTD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	{0,	INTA1,	INTC,  INTD,  INTB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	{0,	INTA2,	INTD,  INTB,  INTC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * the device (1-4 => A-D), tell what irq to use.  Note that we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * in theory have slots 4 and 5, and we never normally use the shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * irqs.  I suppose a device without a pin A will thank us for doing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * right if there exists such a broken piece of crap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return irq_tab_mace[slot][pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }