^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Cobalt Qube/Raq PCI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/gt64120.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <cobalt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * PCI slot numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define COBALT_PCICONF_CPU 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define COBALT_PCICONF_ETH0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define COBALT_PCICONF_RAQSCSI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define COBALT_PCICONF_VIA 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define COBALT_PCICONF_PCISLOT 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define COBALT_PCICONF_ETH1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The Cobalt board ID information. The boards have an ID number wired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * into the VIA that is available in the high nibble of register 94.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIA_COBALT_BRD_ID_REG 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (dev->devfn == PCI_DEVFN(0, 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) printk(KERN_INFO "Galileo: fixed bridge class\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) qube_raq_galileo_early_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned short cfgword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char lt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Enable Bus Mastering and fast back to back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pci_read_config_word(dev, PCI_COMMAND, &cfgword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_write_config_word(dev, PCI_COMMAND, cfgword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Enable both ide interfaces. ROM only enables primary one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pci_write_config_byte(dev, 0x40, 0xb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Set latency timer to reasonable value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (lt < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) qube_raq_via_bmIDE_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void qube_raq_galileo_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (dev->devfn != PCI_DEVFN(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Fix PCI latency-timer and cache-line-size values in Galileo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * host bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * The code described by the comment below has been removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * as it causes bus mastering by the Ethernet controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * to break under any kind of network load. We always set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * the retry timeouts to their maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * On all machines prior to Q2, we had the STOP line disconnected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * from Galileo to VIA on PCI. The new Galileo does not function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * correctly unless we have it connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Therefore we must set the disconnect/retry cycle values to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * something sensible when using the new Galileo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (dev->revision >= 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* New Galileo, assumes PCI stop line to VIA is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } else if (dev->revision == 0x1 || dev->revision == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) signed int timeo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) timeo = GT_READ(GT_PCI0_TOR_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GT_WRITE(GT_PCI0_TOR_OFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (0xff << 16) | /* retry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (0xff << 8) | /* timeout 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0xff); /* timeout 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* enable PCI retry exceeded interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) qube_raq_galileo_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int cobalt_board_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) panic("Cannot read board ID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) qube_raq_via_board_id_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static char irq_tab_qube1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [COBALT_PCICONF_CPU] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [COBALT_PCICONF_VIA] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [COBALT_PCICONF_ETH1] = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static char irq_tab_cobalt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [COBALT_PCICONF_CPU] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [COBALT_PCICONF_ETH0] = ETH0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [COBALT_PCICONF_VIA] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [COBALT_PCICONF_ETH1] = ETH1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static char irq_tab_raq2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [COBALT_PCICONF_CPU] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [COBALT_PCICONF_ETH0] = ETH0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [COBALT_PCICONF_VIA] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [COBALT_PCICONF_ETH1] = ETH1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return irq_tab_qube1[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return irq_tab_raq2[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return irq_tab_cobalt[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Do platform specific device initialization at pci_enable_device() time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int pcibios_plat_dev_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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