Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2003-2012 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * licenses.  You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * General Public License (GPL) Version 2, available from the file
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <asm/netlogic/xlr/fmn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <asm/netlogic/xlr/xlr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct xlr_board_fmn_config xlr_board_fmn_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void __maybe_unused print_credit_config(struct xlr_fmn_info *fmn_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int bkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	pr_info("Bucket size :\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	pr_info("Station\t: Size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	for (bkt = 0; bkt < 16; bkt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		pr_info(" %d  %d  %d  %d  %d  %d  %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			xlr_board_fmn_config.bucket_size[(bkt * 8) + 7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pr_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	pr_info("Credits distribution :\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	pr_info("Station\t: Size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	for (bkt = 0; bkt < 16; bkt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		pr_info(" %d  %d  %d  %d  %d  %d  %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			fmn_info->credit_config[(bkt * 8) + 0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			fmn_info->credit_config[(bkt * 8) + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			fmn_info->credit_config[(bkt * 8) + 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			fmn_info->credit_config[(bkt * 8) + 3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			fmn_info->credit_config[(bkt * 8) + 4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			fmn_info->credit_config[(bkt * 8) + 5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			fmn_info->credit_config[(bkt * 8) + 6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			fmn_info->credit_config[(bkt * 8) + 7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	pr_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void check_credit_distribution(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct xlr_board_fmn_config *cfg = &xlr_board_fmn_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int bkt, n, total_credits, ncores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ncores = hweight32(nlm_current_node()->coremask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	for (bkt = 0; bkt < 128; bkt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		total_credits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		for (n = 0; n < ncores; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			total_credits += cfg->cpu[n].credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		total_credits += cfg->gmac[0].credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		total_credits += cfg->gmac[1].credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		total_credits += cfg->dma.credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		total_credits += cfg->cmp.credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		total_credits += cfg->sae.credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		total_credits += cfg->xgmac[0].credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		total_credits += cfg->xgmac[1].credit_config[bkt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (total_credits > cfg->bucket_size[bkt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			pr_err("ERROR: Bucket %d: credits (%d) > size (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				bkt, total_credits, cfg->bucket_size[bkt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	pr_info("Credit distribution complete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * Configure bucket size and credits for a device. 'size' is the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * the buckets for the device. This size is distributed among all the CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * so that all of them can send messages to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * The device is also given 'cpu_credits' to send messages to the CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * @dev_info: FMN information structure for each devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * @start_stn_id: Starting station id of dev_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * @end_stn_id: End station id of dev_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * @num_buckets: Total number of buckets for den_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * @cpu_credits: Allowed credits to cpu for each devices pointing by dev_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * @size: Size of the each buckets in the device station
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void setup_fmn_cc(struct xlr_fmn_info *dev_info, int start_stn_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		int end_stn_id, int num_buckets, int cpu_credits, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int i, j, num_core, n, credits_per_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	num_core = hweight32(nlm_current_node()->coremask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	dev_info->num_buckets	= num_buckets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	dev_info->start_stn_id	= start_stn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	dev_info->end_stn_id	= end_stn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	n = num_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (num_core == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		n = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (i = start_stn_id; i <= end_stn_id; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		xlr_board_fmn_config.bucket_size[i] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* Dividing device credits equally to cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		credits_per_cpu = size / n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		for (j = 0; j < num_core; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			cpu[j].credit_config[i] = credits_per_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* credits left to distribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		credits_per_cpu = size - (credits_per_cpu * num_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		/* distribute the remaining credits (if any), among cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		for (j = 0; (j < num_core) && (credits_per_cpu >= 4); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			cpu[j].credit_config[i] += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			credits_per_cpu -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* Distributing cpu per bucket credits to devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	for (i = 0; i < num_core; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		for (j = 0; j < FMN_CORE_NBUCKETS; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			dev_info->credit_config[(i * 8) + j] = cpu_credits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * Each core has 256 slots and 8 buckets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * Configure the 8 buckets each with 32 slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void setup_cpu_fmninfo(struct xlr_fmn_info *cpu, int num_core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 0; i < num_core; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		cpu[i].start_stn_id	= (8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		cpu[i].end_stn_id	= (8 * i + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			xlr_board_fmn_config.bucket_size[j] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * Setup the FMN details for each devices according to the device available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * in each variant of XLR/XLS processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void xlr_board_info_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct xlr_fmn_info *gmac = xlr_board_fmn_config.gmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct xlr_fmn_info *xgmac = xlr_board_fmn_config.xgmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct xlr_fmn_info *dma = &xlr_board_fmn_config.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct xlr_fmn_info *cmp = &xlr_board_fmn_config.cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct xlr_fmn_info *sae = &xlr_board_fmn_config.sae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int processor_id, num_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	num_core = hweight32(nlm_current_node()->coremask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	processor_id = read_c0_prid() & PRID_IMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	setup_cpu_fmninfo(cpu, num_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	switch (processor_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case PRID_IMP_NETLOGIC_XLS104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case PRID_IMP_NETLOGIC_XLS108:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					FMN_STNID_GMAC0_TX3, 8, 16, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 					FMN_STNID_DMA_3, 4, 8, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 					FMN_STNID_SEC1, 2, 8, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case PRID_IMP_NETLOGIC_XLS204:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case PRID_IMP_NETLOGIC_XLS208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					FMN_STNID_GMAC0_TX3, 8, 16, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 					FMN_STNID_DMA_3, 4, 8, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					FMN_STNID_SEC1, 2, 8, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case PRID_IMP_NETLOGIC_XLS404:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case PRID_IMP_NETLOGIC_XLS408:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case PRID_IMP_NETLOGIC_XLS404B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case PRID_IMP_NETLOGIC_XLS408B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case PRID_IMP_NETLOGIC_XLS416B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case PRID_IMP_NETLOGIC_XLS608B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case PRID_IMP_NETLOGIC_XLS616B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					FMN_STNID_GMAC0_TX3, 8, 8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					FMN_STNID_GMAC1_TX3, 8, 8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					FMN_STNID_DMA_3, 4, 4, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		setup_fmn_cc(cmp, FMN_STNID_CMP_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 					FMN_STNID_CMP_3, 4, 4, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					FMN_STNID_SEC1, 2, 8, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case PRID_IMP_NETLOGIC_XLS412B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					FMN_STNID_GMAC0_TX3, 8, 8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					FMN_STNID_GMAC1_TX3, 8, 8, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					FMN_STNID_DMA_3, 4, 4, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		setup_fmn_cc(cmp, FMN_STNID_CMP_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					FMN_STNID_CMP_3, 4, 4, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 					FMN_STNID_SEC1, 2, 8, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	case PRID_IMP_NETLOGIC_XLR308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case PRID_IMP_NETLOGIC_XLR308C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					FMN_STNID_GMAC0_TX3, 8, 16, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 					FMN_STNID_DMA_3, 4, 8, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 					FMN_STNID_SEC1, 2, 4, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case PRID_IMP_NETLOGIC_XLR532:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case PRID_IMP_NETLOGIC_XLR532C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case PRID_IMP_NETLOGIC_XLR516C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case PRID_IMP_NETLOGIC_XLR508C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					FMN_STNID_GMAC0_TX3, 8, 16, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 					FMN_STNID_DMA_3, 4, 8, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					FMN_STNID_SEC1, 2, 4, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case PRID_IMP_NETLOGIC_XLR732:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case PRID_IMP_NETLOGIC_XLR716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		setup_fmn_cc(&xgmac[0], FMN_STNID_XMAC0_00_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					FMN_STNID_XMAC0_15_TX, 8, 0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		setup_fmn_cc(&xgmac[1], FMN_STNID_XMAC1_00_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					FMN_STNID_XMAC1_15_TX, 8, 0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 					FMN_STNID_GMAC0_TX3, 8, 24, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		setup_fmn_cc(dma, FMN_STNID_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 					FMN_STNID_DMA_3, 4, 4, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		setup_fmn_cc(sae, FMN_STNID_SEC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					FMN_STNID_SEC1, 2, 4, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		pr_err("Unknown CPU with processor ID [%d]\n", processor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		pr_err("Error: Cannot initialize FMN credits.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	check_credit_distribution();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #if 0 /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	print_credit_config(&cpu[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	print_credit_config(&gmac[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }