^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the NetLogic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/netlogic/mips-extns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/netlogic/xlp-hal/pic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/netlogic/xlp-hal/sys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint32_t coremask, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int count, resetreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) coremask = (1 << core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Enable CPU clock in case of 8xx/3xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!cpu_is_xlpii()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) value &= ~coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* On 9XX, mark coherent first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) value &= ~coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Remove CPU Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) value = nlm_read_sys_reg(sysbase, resetreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) value &= ~coremask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) nlm_write_sys_reg(sysbase, resetreg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* We are done on 9XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (cpu_is_xlp9xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Poll for CPU to mark itself coherent on other type of XLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) count = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } while ((value & coremask) != 0 && --count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return count != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int wait_for_cpus(int cpu, int bootcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int i, count, notready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) count = 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) notready = nlm_threads_per_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) for (i = 0; i < nlm_threads_per_core; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) --notready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } while (notready != 0 && --count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return count != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct nlm_soc_info *nodep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint64_t syspcibase, fusebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) uint32_t syscoremask, mask, fusemask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int core, n, cpu, ncores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (n = 0; n < NLM_NR_NODES; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (n != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* check if node exists and is online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int b = xlp9xx_get_socbus(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_info("Node %d SoC PCI bus %d.\n", n, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (b == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) syspcibase = nlm_get_sys_pcibase(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) nlm_node_init(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* read cores in reset from SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) nodep = nlm_get_node(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) fusebase = nlm_get_fuse_regbase(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (read_c0_prid() & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case PRID_IMP_NETLOGIC_XLP5XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case PRID_IMP_NETLOGIC_XLP9XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mask = 0xfffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) fusemask = nlm_read_sys_reg(nodep->sysbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SYS_EFUSE_DEVICE_CFG_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (read_c0_prid() & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case PRID_IMP_NETLOGIC_XLP3XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case PRID_IMP_NETLOGIC_XLP2XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mask = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case PRID_IMP_NETLOGIC_XLP8XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Fused out cores are set in the fusemask, and the remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * cores are renumbered to range 0 .. nactive-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ncores = nlm_cores_per_node();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (core = 0; core < ncores; core++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* we will be on node 0 core 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (n == 0 && core == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* see if the core exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if ((syscoremask & (1 << core)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* see if at least the first hw thread is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!cpumask_test_cpu(cpu, wakeup_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* wake up the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!xlp_wakeup_core(nodep->sysbase, n, core))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* core is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) nodep->coremask |= 1u << core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* spin until the hw threads sets their ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!wait_for_cpus(cpu, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("Node %d : timeout core %d\n", n, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void xlp_wakeup_secondary_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * In case of u-boot, the secondaries are in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * first wakeup core 0 threads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) xlp_boot_core0_siblings();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!wait_for_cpus(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_err("Node 0 : timeout core 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* now get other cores out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) xlp_enable_secondary_cores(&nlm_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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