^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2003-2012 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licenses. You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * COPYING in the main directory of this source tree, or the Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * USB glue logic registers, used only during initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_CTL_0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USB_PHY_0 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB_PHY_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB_PHY_PORT_RESET_0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USB_PHY_PORT_RESET_1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB_CONTROLLER_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USB_INT_STATUS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USB_INT_EN 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USB_PHY_INTERRUPT_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB_OHCI_INTERRUPT_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB_OHCI_INTERRUPT1_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USB_OHCI_INTERRUPT2_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB_CTRL_INTERRUPT_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define nlm_get_usb_pcibase(node, inst) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define nlm_get_usb_regbase(node, inst) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void nlm_usb_intr_en(int node, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) uint64_t port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) port_addr = nlm_get_usb_regbase(node, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = nlm_read_usb_reg(port_addr, USB_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) nlm_write_usb_reg(port_addr, USB_INT_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void nlm_usb_hw_reset(int node, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint64_t port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* reset USB phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) port_addr = nlm_get_usb_regbase(node, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = nlm_read_usb_reg(port_addr, USB_PHY_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) nlm_write_usb_reg(port_addr, USB_PHY_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = nlm_read_usb_reg(port_addr, USB_CTL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val &= ~(USB_CONTROLLER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) nlm_write_usb_reg(port_addr, USB_CTL_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int __init nlm_platform_usb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (cpu_is_xlpii())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_info("Initializing USB Interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) nlm_usb_hw_reset(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) nlm_usb_hw_reset(0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Enable PHY interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) nlm_usb_intr_en(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) nlm_usb_intr_en(0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) arch_initcall(nlm_platform_usb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u64 xlp_usb_dmamask = ~(u32)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void nlm_usb_fixup_final(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev->dev.dma_mask = &xlp_usb_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (dev->devfn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev->irq = PIC_EHCI_0_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 0x11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev->irq = PIC_OHCI_0_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev->irq = PIC_OHCI_1_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 0x13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev->irq = PIC_EHCI_1_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev->irq = PIC_OHCI_2_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev->irq = PIC_OHCI_3_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) nlm_usb_fixup_final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) nlm_usb_fixup_final);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags