Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2003-2013 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * licenses.  You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * COPYING in the main directory of this source tree, or the Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * modification, are permitted provided that the following conditions
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    notice, this list of conditions and the following disclaimer.
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *    notice, this list of conditions and the following disclaimer in
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define XLPII_USB3_CTL_0		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define XLPII_VAUXRST			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define XLPII_VCCRST			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define XLPII_NUM2PORT			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define XLPII_NUM3PORT			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define XLPII_RTUNEREQ			BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define XLPII_MS_CSYSREQ		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define XLPII_XS_CSYSREQ		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define XLPII_RETENABLEN		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define XLPII_TX2RX			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define XLPII_XHCIREV			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define XLPII_ECCDIS			BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define XLPII_USB3_INT_REG		0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define XLPII_USB3_INT_MASK		0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define XLPII_USB_PHY_TEST		0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define XLPII_PRESET			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define XLPII_ATERESET			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define XLPII_LOOPEN			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define XLPII_TESTPDHSP			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define XLPII_TESTPDSSP			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define XLPII_TESTBURNIN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define XLPII_USB_PHY_LOS_LV		0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define XLPII_LOSLEV			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define XLPII_LOSBIAS			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define XLPII_SQRXTX			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define XLPII_TXBOOST			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define XLPII_RSLKSEL			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define XLPII_FSEL			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define XLPII_USB_RFCLK_REG		0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define XLPII_VVLD			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define nlm_read_usb_reg(b, r)		nlm_read_reg(b, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define nlm_write_usb_reg(b, r, v)	nlm_write_reg(b, r, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define nlm_xlpii_get_usb_pcibase(node, inst)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			nlm_pcicfg_base(cpu_is_xlp9xx() ?	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			XLP9XX_IO_USB_OFFSET(node, inst) :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			XLP2XX_IO_USB_OFFSET(node, inst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define nlm_xlpii_get_usb_regbase(node, inst)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	(nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void xlp2xx_usb_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u64 port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case PIC_2XX_XHCI_0_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		port_addr = nlm_xlpii_get_usb_regbase(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case PIC_2XX_XHCI_1_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		port_addr = nlm_xlpii_get_usb_regbase(0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case PIC_2XX_XHCI_2_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		port_addr = nlm_xlpii_get_usb_regbase(0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		pr_err("No matching USB irq!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void xlp9xx_usb_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u64 port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int node, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Find the node and irq on the node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	irq = data->irq % NLM_IRQS_PER_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	node = data->irq / NLM_IRQS_PER_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	switch (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case PIC_9XX_XHCI_0_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		port_addr = nlm_xlpii_get_usb_regbase(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case PIC_9XX_XHCI_1_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		port_addr = nlm_xlpii_get_usb_regbase(node, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case PIC_9XX_XHCI_2_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		port_addr = nlm_xlpii_get_usb_regbase(node, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		pr_err("No matching USB irq %d node  %d!\n", irq, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void nlm_xlpii_usb_hw_reset(int node, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u64 port_addr, xhci_base, pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	void __iomem *corebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	port_addr = nlm_xlpii_get_usb_regbase(node, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* Set frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	val &= ~(0x3f << XLPII_FSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	val |= (0x27 << XLPII_FSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	val |= (1 << XLPII_VVLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		| XLPII_TESTPDSSP | XLPII_TESTBURNIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Setup control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	val =  XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		| (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		| XLPII_RETENABLEN | XLPII_XHCIREV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	udelay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* XHCI configuration at PCI mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	pci_base = nlm_xlpii_get_usb_pcibase(node, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	corebase = ioremap(xhci_base, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!corebase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	writel(0x240002, corebase + 0xc2c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* GCTL 0xc110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	val = readl(corebase + 0xc110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	val &= ~(0x3 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	val |= (1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	writel(val, corebase + 0xc110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* PHYCFG 0xc200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	val = readl(corebase + 0xc200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	val &= ~(1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	writel(val, corebase + 0xc200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* PIPECTL 0xc2c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	val = readl(corebase + 0xc2c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	val &= ~(1 << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	writel(val, corebase + 0xc2c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	iounmap(corebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int __init nlm_platform_xlpii_usb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!cpu_is_xlpii())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!cpu_is_xlp9xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		/* XLP 2XX single node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		pr_info("Initializing 2XX USB Interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		nlm_xlpii_usb_hw_reset(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		nlm_xlpii_usb_hw_reset(0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		nlm_xlpii_usb_hw_reset(0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* XLP 9XX, multi-node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	pr_info("Initializing 9XX/5XX USB Interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	for (node = 0; node < NLM_NR_NODES; node++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (!nlm_node_present(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		nlm_xlpii_usb_hw_reset(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		nlm_xlpii_usb_hw_reset(node, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		nlm_xlpii_usb_hw_reset(node, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) arch_initcall(nlm_platform_xlpii_usb_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u64 xlp_usb_dmamask = ~(u32)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	node = xlp_socdev_to_node(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	dev->dev.dma_mask		= &xlp_usb_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dev->dev.coherent_dma_mask	= DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	switch (dev->devfn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case 0x21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case 0x22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	case 0x23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dev->dev.dma_mask		= &xlp_usb_dmamask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	dev->dev.coherent_dma_mask	= DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	switch (dev->devfn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case 0x21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dev->irq = PIC_2XX_XHCI_0_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	case 0x22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		dev->irq = PIC_2XX_XHCI_1_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	case 0x23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		dev->irq = PIC_2XX_XHCI_2_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		nlm_xlp9xx_usb_fixup_final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		nlm_xlp2xx_usb_fixup_final);