^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Broadcom Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on arch/mips/cavium-octeon/cpu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009 Wind River Systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * written by Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cop2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/current.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/netlogic/mips-extns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 64 bit ops are done in inline assembly to support 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * compilation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void nlm_cop2_save(struct nlm_cop2_state *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ".set push\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ".set noat\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "dmfc2 $1, $0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "sd $1, 0(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "dmfc2 $1, $0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "sd $1, 8(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "dmfc2 $1, $0, 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "sd $1, 16(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "dmfc2 $1, $0, 3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "sd $1, 24(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "dmfc2 $1, $1, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "sd $1, 0(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "dmfc2 $1, $1, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "sd $1, 8(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "dmfc2 $1, $1, 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "sd $1, 16(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "dmfc2 $1, $1, 3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "sd $1, 24(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ".set pop\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) : "=m"(*r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) : "r"(r->tx), "r"(r->rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) r->tx_msg_status = __read_32bit_c2_register($2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void nlm_cop2_restore(struct nlm_cop2_state *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 rstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ".set push\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ".set noat\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "ld $1, 0(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "dmtc2 $1, $0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "ld $1, 8(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "dmtc2 $1, $0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "ld $1, 16(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "dmtc2 $1, $0, 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "ld $1, 24(%1)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "dmtc2 $1, $0, 3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "ld $1, 0(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "dmtc2 $1, $1, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "ld $1, 8(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "dmtc2 $1, $1, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "ld $1, 16(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dmtc2 $1, $1, 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "ld $1, 24(%2)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "dmtc2 $1, $1, 3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ".set pop\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) : : "m"(*r), "r"(r->tx), "r"(r->rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __write_32bit_c2_register($2, 0, r->tx_msg_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case CU2_EXCEPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) KSTK_STATUS(current) |= ST0_CU2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) status = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) write_c0_status(status | ST0_CU2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) nlm_cop2_restore(&(current->thread.cp2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) write_c0_status(status & ~ST0_CU2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_info("COP2 access enabled for pid %d (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) current->pid, current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return NOTIFY_BAD; /* Don't call default notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return NOTIFY_OK; /* Let default notifier send signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int __init nlm_cu2_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return cu2_notifier(nlm_cu2_call, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) early_initcall(nlm_cu2_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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