Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2003-2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This software is available to you under a choice of one of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * licenses.  You may choose to be licensed under the terms of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * General Public License (GPL) Version 2, available from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * COPYING in the main directory of this source tree, or the Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * license below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * modification, are permitted provided that the following conditions
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *    notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *    the documentation and/or other materials provided with the
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <asm/netlogic/haldefs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <asm/netlogic/xlp-hal/xlp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <asm/netlogic/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <asm/netlogic/xlp-hal/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <asm/netlogic/mips-extns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SATA_CTL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SATA_STATUS		0x1	/* Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SATA_INT		0x2	/* Interrupt Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SATA_INT_MASK		0x3	/* Interrupt Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SATA_CR_REG_TIMER	0x4	/* PHY Conrol Timer Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SATA_CORE_ID		0x5	/* Core ID Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SATA_AXI_SLAVE_OPT1	0x6	/* AXI Slave Options Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SATA_PHY_LOS_LEV	0x7	/* PHY LOS Level Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SATA_PHY_MULTI		0x8	/* PHY Multiplier Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SATA_PHY_CLK_SEL	0x9	/* Clock Select Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SATA_PHY_AMP1_GEN1	0xa	/* PHY Transmit Amplitude Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SATA_PHY_AMP1_GEN2	0xb	/* PHY Transmit Amplitude Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SATA_PHY_AMP1_GEN3	0xc	/* PHY Transmit Amplitude Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SATA_PHY_PRE1		0xd	/* PHY Transmit Preemphasis Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SATA_PHY_PRE2		0xe	/* PHY Transmit Preemphasis Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SATA_PHY_PRE3		0xf	/* PHY Transmit Preemphasis Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SATA_SPDMODE		0x10	/* Speed Mode Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SATA_REFCLK		0x11	/* Reference Clock Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SATA_BYTE_SWAP_DIS	0x12	/* byte swap disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /*SATA_CTL Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SATA_RST_N		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PHY0_RESET_N		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PHY1_RESET_N		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PHY2_RESET_N		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PHY3_RESET_N		BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define M_CSYSREQ		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define S_CSYSREQ		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*SATA_STATUS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define P0_PHY_READY		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define P1_PHY_READY		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define P2_PHY_READY		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define P3_PHY_READY		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define nlm_read_sata_reg(b, r)		nlm_read_reg(b, r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define nlm_write_sata_reg(b, r, v)	nlm_write_reg(b, r, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define nlm_get_sata_pcibase(node)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		nlm_pcicfg_base(XLP_IO_SATA_OFFSET(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* SATA device specific configuration registers are starts at 0x900 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define nlm_get_sata_regbase(node)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		(nlm_get_sata_pcibase(node) + 0x900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	uint32_t reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	reg_val = nlm_read_sata_reg(regbase, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	nlm_write_sata_reg(regbase, off, (reg_val & ~bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	uint32_t reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	reg_val = nlm_read_sata_reg(regbase, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	nlm_write_sata_reg(regbase, off, (reg_val | bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void nlm_sata_firmware_init(int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	uint32_t reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uint64_t regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	pr_info("XLP AHCI Initialization started.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regbase = nlm_get_sata_regbase(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Reset SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	sata_clear_glue_reg(regbase, SATA_CTL, SATA_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Reset PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	sata_clear_glue_reg(regbase, SATA_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			(PHY3_RESET_N | PHY2_RESET_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			 | PHY1_RESET_N | PHY0_RESET_N));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* Set SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* Set PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sata_set_glue_reg(regbase, SATA_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			(PHY3_RESET_N | PHY2_RESET_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			 | PHY1_RESET_N | PHY0_RESET_N));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pr_debug("Waiting for PHYs to come up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		reg_val = nlm_read_sata_reg(regbase, SATA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} while (((reg_val & 0xF0) != 0xF0) && (i < 10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (reg_val  & (P0_PHY_READY << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			pr_info("PHY%d is up.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			pr_info("PHY%d is down.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	pr_info("XLP AHCI init done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __init nlm_ahci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int chip = read_c0_prid() & PRID_IMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (chip == PRID_IMP_NETLOGIC_XLP3XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		nlm_sata_firmware_init(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void nlm_sata_intr_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	uint32_t val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	uint64_t regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	regbase = nlm_get_sata_regbase(nlm_nodeid());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	val = nlm_read_sata_reg(regbase, SATA_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	sata_set_glue_reg(regbase, SATA_INT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void nlm_sata_fixup_bar(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * The AHCI resource is in BAR 0, move it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * BAR 5, where it is expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dev->resource[5] = dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void nlm_sata_fixup_final(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	uint64_t regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int node = 0; /* XLP3XX does not support multi-node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	regbase = nlm_get_sata_regbase(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* clear pending interrupts and then enable them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	val = nlm_read_sata_reg(regbase, SATA_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	sata_set_glue_reg(regbase, SATA_INT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* Mask the core interrupt. If all the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * are enabled there are spurious interrupt flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * happening, to avoid only enable core interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	dev->irq = PIC_SATA_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) arch_initcall(nlm_ahci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		nlm_sata_fixup_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		nlm_sata_fixup_final);