^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Just-In-Time compiler for BPF filters on MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Markos Chandras <markos.chandras@imgtec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef BPF_JIT_MIPS_OP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BPF_JIT_MIPS_OP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Registers used by JIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MIPS_R_ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MIPS_R_V0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MIPS_R_A0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MIPS_R_A1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MIPS_R_T4 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MIPS_R_T5 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MIPS_R_T6 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MIPS_R_T7 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MIPS_R_S0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MIPS_R_S1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MIPS_R_S2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MIPS_R_S3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MIPS_R_S4 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MIPS_R_S5 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MIPS_R_S6 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MIPS_R_S7 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MIPS_R_SP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MIPS_R_RA 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Conditional codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MIPS_COND_EQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MIPS_COND_GE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MIPS_COND_GT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MIPS_COND_NE (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MIPS_COND_ALL (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Conditionals on X register or K immediate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIPS_COND_X (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MIPS_COND_K (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define r_ret MIPS_R_V0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Use 2 scratch registers to avoid pipeline interlocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * There is no overhead during epilogue and prologue since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * any of the $s0-$s6 registers will only be preserved if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * they are going to actually be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define r_skb_hl MIPS_R_S0 /* skb header length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define r_skb_data MIPS_R_S1 /* skb actual data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define r_off MIPS_R_S2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define r_A MIPS_R_S3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define r_X MIPS_R_S4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define r_skb MIPS_R_S5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define r_M MIPS_R_S6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define r_skb_len MIPS_R_S7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define r_s0 MIPS_R_T4 /* scratch reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define r_s1 MIPS_R_T5 /* scratch reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define r_tmp MIPS_R_T7 /* No need to preserve this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define r_zero MIPS_R_ZERO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define r_sp MIPS_R_SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define r_ra MIPS_R_RA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Declare ASM helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DECLARE_LOAD_FUNC(func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern u8 func(unsigned long *skb, int offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern u8 func##_negative(unsigned long *skb, int offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern u8 func##_positive(unsigned long *skb, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DECLARE_LOAD_FUNC(sk_load_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DECLARE_LOAD_FUNC(sk_load_half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DECLARE_LOAD_FUNC(sk_load_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* BPF_JIT_MIPS_OP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags