^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * A small micro-assembler. It is intentionally kept simple, does only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * support a subset of instructions, and does not try to hide pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * effects like branch delay slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2005, 2007 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) RS = 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) RT = 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) RD = 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RE = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SIMM = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) UIMM = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) BIMM = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) JIMM = 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FUNC = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SET = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SCIMM = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SIMM9 = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OP_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OP_SH 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RD_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RD_SH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RE_SH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMM_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMM_SH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JIMM_MASK 0x3ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JIMM_SH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FUNC_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FUNC_SH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SET_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SET_SH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIMM9_SH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIMM9_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) insn_wsbh, insn_xor, insn_xori, insn_yield,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) insn_invalid /* insn_invalid must be last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct insn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum fields fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline u32 build_rs(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return (arg & RS_MASK) << RS_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u32 build_rt(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return (arg & RT_MASK) << RT_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline u32 build_rd(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (arg & RD_MASK) << RD_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline u32 build_re(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return (arg & RE_MASK) << RE_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline u32 build_simm(s32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) WARN(arg > 0x7fff || arg < -0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return arg & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline u32 build_uimm(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return arg & IMM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline u32 build_scimm(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) WARN(arg & ~SCIMM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return (arg & SCIMM_MASK) << SCIMM_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline u32 build_scimm9(s32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) WARN((arg > 0xff || arg < -0x100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return (arg & SIMM9_MASK) << SIMM9_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline u32 build_func(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return arg & FUNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline u32 build_set(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return arg & SET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void build_insn(u32 **buf, enum opcode opc, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define I_u1u2u3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Ip_u1u2u3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) build_insn(buf, insn##op, a, b, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define I_s3s1s2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) Ip_s3s1s2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) build_insn(buf, insn##op, b, c, a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define I_u2u1u3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Ip_u2u1u3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) build_insn(buf, insn##op, b, a, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define I_u3u2u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Ip_u3u2u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) build_insn(buf, insn##op, c, b, a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define I_u3u1u2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Ip_u3u1u2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) build_insn(buf, insn##op, b, c, a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define I_u1u2s3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Ip_u1u2s3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) build_insn(buf, insn##op, a, b, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define I_u2s3u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Ip_u2s3u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) build_insn(buf, insn##op, c, a, b); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define I_u2u1s3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) Ip_u2u1s3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) build_insn(buf, insn##op, b, a, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define I_u2u1msbu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) Ip_u2u1msbu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) build_insn(buf, insn##op, b, a, c+d-1, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define I_u2u1msb32u3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) Ip_u2u1msbu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) build_insn(buf, insn##op, b, a, c+d-33, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define I_u2u1msb32msb3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) Ip_u2u1msbu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) build_insn(buf, insn##op, b, a, c+d-33, c-32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define I_u2u1msbdu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) Ip_u2u1msbu3(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) build_insn(buf, insn##op, b, a, d-1, c); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define I_u1u2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) Ip_u1u2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) build_insn(buf, insn##op, a, b); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define I_u2u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) Ip_u1u2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) build_insn(buf, insn##op, b, a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define I_u1s2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) Ip_u1s2(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) build_insn(buf, insn##op, a, b); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define I_u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) Ip_u1(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) build_insn(buf, insn##op, a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define I_0(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) Ip_0(op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) build_insn(buf, insn##op); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) UASM_EXPORT_SYMBOL(uasm_i##op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) I_u2u1s3(_addiu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) I_u3u1u2(_addu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) I_u2u1u3(_andi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) I_u3u1u2(_and)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) I_u1u2s3(_beq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) I_u1u2s3(_beql)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) I_u1s2(_bgez)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) I_u1s2(_bgezl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) I_u1s2(_bgtz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) I_u1s2(_blez)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) I_u1s2(_bltz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) I_u1s2(_bltzl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) I_u1u2s3(_bne)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) I_u1(_break)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) I_u2s3u1(_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) I_u1u2(_cfc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) I_u2u1(_cfcmsa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) I_u1u2(_ctc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) I_u2u1(_ctcmsa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) I_u1u2(_ddivu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) I_u3u1u2(_ddivu_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) I_u1u2u3(_dmfc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) I_u3u1u2(_dmodu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) I_u1u2u3(_dmtc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) I_u1u2(_dmultu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) I_u3u1u2(_dmulu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) I_u2u1s3(_daddiu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) I_u3u1u2(_daddu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) I_u1(_di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) I_u1u2(_divu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) I_u3u1u2(_divu_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) I_u2u1(_dsbh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) I_u2u1(_dshd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) I_u2u1u3(_dsll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) I_u2u1u3(_dsll32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) I_u3u2u1(_dsllv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) I_u2u1u3(_dsra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) I_u2u1u3(_dsra32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) I_u3u2u1(_dsrav)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) I_u2u1u3(_dsrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) I_u2u1u3(_dsrl32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) I_u3u2u1(_dsrlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) I_u2u1u3(_drotr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) I_u2u1u3(_drotr32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) I_u3u1u2(_dsubu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) I_0(_eret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) I_u2u1msbdu3(_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) I_u2u1msbu3(_ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) I_u1(_j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) I_u1(_jal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I_u2u1(_jalr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) I_u1(_jr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) I_u2s3u1(_lb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) I_u2s3u1(_lbu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) I_u2s3u1(_ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) I_u2s3u1(_lh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) I_u2s3u1(_lhu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) I_u2s3u1(_ll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) I_u2s3u1(_lld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) I_u1s2(_lui)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) I_u2s3u1(_lw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) I_u2s3u1(_lwu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) I_u1u2u3(_mfc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) I_u1u2u3(_mfhc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) I_u3u1u2(_modu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) I_u3u1u2(_movn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) I_u3u1u2(_movz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) I_u1(_mfhi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) I_u1(_mflo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) I_u1u2u3(_mtc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) I_u1u2u3(_mthc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) I_u1(_mthi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) I_u1(_mtlo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) I_u3u1u2(_mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) I_u1u2(_multu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) I_u3u1u2(_mulu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) I_u3u1u2(_nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) I_u3u1u2(_or)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) I_u2u1u3(_ori)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) I_0(_rfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) I_u2s3u1(_sb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) I_u2s3u1(_sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) I_u2s3u1(_scd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) I_u2s3u1(_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) I_u3u1u2(_seleqz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) I_u3u1u2(_selnez)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) I_u2s3u1(_sh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) I_u2u1u3(_sll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) I_u3u2u1(_sllv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) I_s3s1s2(_slt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) I_u2u1s3(_slti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) I_u2u1s3(_sltiu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) I_u3u1u2(_sltu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) I_u2u1u3(_sra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) I_u3u2u1(_srav)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) I_u2u1u3(_srl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) I_u3u2u1(_srlv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) I_u2u1u3(_rotr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) I_u3u1u2(_subu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) I_u2s3u1(_sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) I_u1(_sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) I_0(_tlbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) I_0(_tlbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) I_0(_tlbwi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) I_0(_tlbwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) I_u1(_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) I_u2u1(_wsbh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) I_u3u1u2(_xor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) I_u2u1u3(_xori)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) I_u2u1(_yield)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) I_u2u1msbu3(_dins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) I_u2u1msb32u3(_dinsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) I_u2u1msb32msb3(_dinsu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) I_u1(_syscall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) I_u1u2s3(_bbit0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) I_u1u2s3(_bbit1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) I_u3u1u2(_lwx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) I_u3u1u2(_ldx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) I_u1u2(_ldpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) I_u2u1u3(_lddir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * As per erratum Core-14449, replace prefetches 0-4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * 6-24 with 'pref 28'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) build_insn(buf, insn_pref, c, 28, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) build_insn(buf, insn_pref, c, a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) UASM_EXPORT_SYMBOL(uasm_i_pref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) I_u2s3u1(_pref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Handle labels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (*lab)->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) (*lab)->lab = lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (*lab)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) UASM_EXPORT_SYMBOL(uasm_build_label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int uasm_in_compat_space_p(long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Is this address in 32bit compat space? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return addr == (int)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int uasm_rel_highest(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int uasm_rel_higher(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int uasm_rel_hi(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) UASM_EXPORT_SYMBOL(uasm_rel_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int uasm_rel_lo(long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ((val & 0xffff) ^ 0x8000) - 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) UASM_EXPORT_SYMBOL(uasm_rel_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!uasm_in_compat_space_p(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uasm_i_lui(buf, rs, uasm_rel_highest(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (uasm_rel_higher(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (uasm_rel_hi(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) uasm_i_dsll(buf, rs, rs, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uasm_i_daddiu(buf, rs, rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uasm_rel_hi(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uasm_i_dsll(buf, rs, rs, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uasm_i_dsll32(buf, rs, rs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) uasm_i_lui(buf, rs, uasm_rel_hi(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) UASM_i_LA_mostly(buf, rs, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (uasm_rel_lo(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!uasm_in_compat_space_p(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uasm_i_daddiu(buf, rs, rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uasm_rel_lo(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uasm_i_addiu(buf, rs, rs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uasm_rel_lo(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) UASM_EXPORT_SYMBOL(UASM_i_LA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Handle relocations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (*rel)->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (*rel)->type = R_MIPS_PC16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (*rel)->lab = lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (*rel)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline void __resolve_relocs(struct uasm_reloc *rel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct uasm_label *lab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void uasm_resolve_relocs(struct uasm_reloc *rel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct uasm_label *lab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct uasm_label *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (; rel->lab != UASM_LABEL_INVALID; rel++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (rel->lab == l->lab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __resolve_relocs(rel, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) long off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (; rel->lab != UASM_LABEL_INVALID; rel++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (rel->addr >= first && rel->addr < end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) rel->addr += off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) UASM_EXPORT_SYMBOL(uasm_move_relocs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) long off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (; lab->lab != UASM_LABEL_INVALID; lab++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (lab->addr >= first && lab->addr < end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) lab->addr += off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) UASM_EXPORT_SYMBOL(uasm_move_labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 *first, u32 *end, u32 *target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) long off = (long)(target - first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) memcpy(target, first, (end - first) * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) uasm_move_relocs(rel, first, end, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uasm_move_labels(lab, first, end, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) UASM_EXPORT_SYMBOL(uasm_copy_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (; rel->lab != UASM_LABEL_INVALID; rel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (rel->addr == addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) && (rel->type == R_MIPS_PC16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) || rel->type == R_MIPS_26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Convenience functions for labeled branches. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) uasm_i_bltz(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) UASM_EXPORT_SYMBOL(uasm_il_bltz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uasm_i_b(p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) UASM_EXPORT_SYMBOL(uasm_il_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int r2, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uasm_i_beq(p, r1, r2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) UASM_EXPORT_SYMBOL(uasm_il_beq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uasm_i_beqz(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) UASM_EXPORT_SYMBOL(uasm_il_beqz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uasm_i_beqzl(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) UASM_EXPORT_SYMBOL(uasm_il_beqzl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned int reg2, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uasm_i_bne(p, reg1, reg2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) UASM_EXPORT_SYMBOL(uasm_il_bne);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) uasm_i_bnez(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) UASM_EXPORT_SYMBOL(uasm_il_bnez);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uasm_i_bgezl(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) UASM_EXPORT_SYMBOL(uasm_il_bgezl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) uasm_i_bgez(p, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) UASM_EXPORT_SYMBOL(uasm_il_bgez);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int bit, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uasm_i_bbit0(p, reg, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) UASM_EXPORT_SYMBOL(uasm_il_bbit0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int bit, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) uasm_r_mips_pc16(r, *p, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uasm_i_bbit1(p, reg, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) UASM_EXPORT_SYMBOL(uasm_il_bbit1);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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