Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * A small micro-assembler. It is intentionally kept simple, does only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * support a subset of instructions, and does not try to hide pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * effects like branch delay slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2005, 2007  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2012, 2013   MIPS Technologies, Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/bugs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/uasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RS_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RS_SH		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RT_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RT_SH		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCIMM_MASK	0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCIMM_SH	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* This macro sets the non-variable bits of an instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define M(a, b, c, d, e, f)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	((a) << OP_SH						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 | (b) << RT_SH						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 | (c) << RS_SH						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	 | (d) << RD_SH						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 | (e) << RE_SH						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	 | (f) << FUNC_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include "uasm.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static const struct insn insn_table_MM[insn_invalid] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	[insn_addu]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[insn_addiu]	= {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	[insn_and]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	[insn_andi]	= {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[insn_beq]	= {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[insn_beql]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[insn_bgez]	= {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[insn_bgezl]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[insn_bltz]	= {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[insn_bltzl]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[insn_bne]	= {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[insn_cache]	= {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[insn_cfc1]	= {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[insn_cfcmsa]	= {M(mm_pool32s_op, 0, msa_cfc_op, 0, 0, mm_32s_elm_op), RD | RE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	[insn_ctc1]	= {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	[insn_ctcmsa]	= {M(mm_pool32s_op, 0, msa_ctc_op, 0, 0, mm_32s_elm_op), RD | RE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[insn_daddu]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[insn_daddiu]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[insn_di]	= {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	[insn_divu]	= {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	[insn_dmfc0]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[insn_dmtc0]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	[insn_dsll]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[insn_dsll32]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	[insn_dsra]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[insn_dsrl]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	[insn_dsrl32]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	[insn_drotr]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[insn_drotr32]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[insn_dsubu]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	[insn_eret]	= {M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[insn_ins]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[insn_ext]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[insn_j]	= {M(mm_j32_op, 0, 0, 0, 0, 0), JIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[insn_jal]	= {M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	[insn_jalr]	= {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	[insn_jr]	= {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[insn_lb]	= {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	[insn_ld]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	[insn_lh]	= {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[insn_ll]	= {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[insn_lld]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	[insn_lui]	= {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[insn_lw]	= {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	[insn_mfc0]	= {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[insn_mfhi]	= {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	[insn_mflo]	= {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	[insn_mtc0]	= {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[insn_mthi]	= {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[insn_mtlo]	= {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	[insn_mul]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[insn_or]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[insn_ori]	= {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[insn_pref]	= {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[insn_rfe]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[insn_sc]	= {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	[insn_scd]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[insn_sd]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[insn_sll]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[insn_sllv]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	[insn_slt]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[insn_sltiu]	= {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	[insn_sltu]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[insn_sra]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	[insn_srav]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[insn_srl]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[insn_srlv]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[insn_rotr]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	[insn_subu]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	[insn_sw]	= {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	[insn_sync]	= {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[insn_tlbp]	= {M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	[insn_tlbr]	= {M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[insn_tlbwi]	= {M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	[insn_tlbwr]	= {M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[insn_wait]	= {M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	[insn_wsbh]	= {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[insn_xor]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[insn_xori]	= {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	[insn_dins]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	[insn_dinsm]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[insn_syscall]	= {M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	[insn_bbit0]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	[insn_bbit1]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	[insn_lwx]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	[insn_ldx]	= {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #undef M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline u32 build_bimm(s32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	WARN(arg > 0xffff || arg < -0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	     KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline u32 build_jimm(u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	WARN(arg & ~((JIMM_MASK << 2) | 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	     KERN_WARNING "Micro-assembler field overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return (arg >> 1) & JIMM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * The order of opcode arguments is implicitly left to right,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * starting with RS and ending with FUNC or IMM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void build_insn(u32 **buf, enum opcode opc, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	const struct insn *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	va_list ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (opc < 0 || opc >= insn_invalid ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	    (opc == insn_daddiu && r4k_daddiu_bug()) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	    (insn_table_MM[opc].match == 0 && insn_table_MM[opc].fields == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		panic("Unsupported Micro-assembler instruction %d", opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ip = &insn_table_MM[opc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	op = ip->match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	va_start(ap, opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ip->fields & RS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (opc == insn_mfc0 || opc == insn_mtc0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		    opc == insn_cfc1 || opc == insn_ctc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			op |= build_rt(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			op |= build_rs(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ip->fields & RT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (opc == insn_mfc0 || opc == insn_mtc0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		    opc == insn_cfc1 || opc == insn_ctc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			op |= build_rs(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			op |= build_rt(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ip->fields & RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		op |= build_rd(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ip->fields & RE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		op |= build_re(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (ip->fields & SIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		op |= build_simm(va_arg(ap, s32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (ip->fields & UIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		op |= build_uimm(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (ip->fields & BIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		op |= build_bimm(va_arg(ap, s32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ip->fields & JIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		op |= build_jimm(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ip->fields & FUNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		op |= build_func(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ip->fields & SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		op |= build_set(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (ip->fields & SCIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		op |= build_scimm(va_arg(ap, u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	va_end(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	**buf = ((op & 0xffff) << 16) | (op >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	**buf = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	(*buf)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	long laddr = (long)lab->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	long raddr = (long)rel->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	switch (rel->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case R_MIPS_PC16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		*rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		*rel->addr |= build_bimm(laddr - (raddr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		panic("Unsupported Micro-assembler relocation %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		      rel->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }