^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Synthesize TLB refill handlers at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2008, 2009 Cavium Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2011 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * ... and the days got worse and worse and now you see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * I've gone completely out of my mind.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * They're coming to take me a away haha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * they're coming to take me a away hoho hihi haha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * to the funny farm where code is beautiful all the time ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * (Condolences to Napoleon XIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/war.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/uasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/tlbex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int mips_xpa_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int __init xpa_disable(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mips_xpa_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __setup("noxpa", xpa_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * TLB load/store/modify handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Only the fastpath gets synthesized at runtime, the slowpath for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * do_page_fault remains normal asm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern void tlb_do_page_fault_0(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern void tlb_do_page_fault_1(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct work_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int r3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct tlb_reg_save {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } ____cacheline_aligned_in_smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct tlb_reg_save handler_reg_save[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline int r45k_bvahwbug(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* XXX: We should probe for the presence of this bug, but we don't. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline int r4k_250MHZhwbug(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* XXX: We should probe for the presence of this bug, but we don't. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern int sb1250_m3_workaround_needed(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline int __maybe_unused bcm1250_m3_war(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return sb1250_m3_workaround_needed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline int __maybe_unused r10000_llsc_war(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int use_bbit_insns(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case CPU_CAVIUM_OCTEON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case CPU_CAVIUM_OCTEON_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case CPU_CAVIUM_OCTEON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case CPU_CAVIUM_OCTEON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int use_lwx_insns(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case CPU_CAVIUM_OCTEON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case CPU_CAVIUM_OCTEON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static bool scratchpad_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int scratchpad_offset(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * CVMSEG starts at address -32768 and extends for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) i += 1; /* Kernel use starts at the top and works down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static bool scratchpad_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int scratchpad_offset(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Really unreachable, but evidently some GCC want this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Found by experiment: At least some revisions of the 4kc throw under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * some circumstances a machine check exception, triggered by invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * values in the index register. Delaying the tlbp instruction until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * after the next branch, plus adding an additional nop in front of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * why; it's not an issue caused by the core RTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int m4kc_tlbp_war(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return current_cpu_type() == CPU_4KC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Handle labels (which must be positive integers). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum label_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) label_second_part = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) label_leave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) label_vmalloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) label_vmalloc_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) label_tlbw_hazard_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) label_split = label_tlbw_hazard_0 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) label_tlbl_goaround1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) label_tlbl_goaround2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) label_nopage_tlbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) label_nopage_tlbs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) label_nopage_tlbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) label_smp_pgtable_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) label_r3000_write_probe_fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) label_large_segbits_fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) label_tlb_huge_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) UASM_L_LA(_second_part)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) UASM_L_LA(_leave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) UASM_L_LA(_vmalloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) UASM_L_LA(_vmalloc_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* _tlbw_hazard_x is handled differently. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) UASM_L_LA(_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) UASM_L_LA(_tlbl_goaround1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) UASM_L_LA(_tlbl_goaround2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) UASM_L_LA(_nopage_tlbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) UASM_L_LA(_nopage_tlbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) UASM_L_LA(_nopage_tlbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) UASM_L_LA(_smp_pgtable_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) UASM_L_LA(_r3000_write_probe_fail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) UASM_L_LA(_large_segbits_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) UASM_L_LA(_tlb_huge_update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int hazard_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case 0 ... 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 0 ... 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * pgtable bits are assigned dynamically depending on processor feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * and statically based on kernel configuration. This spits out the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * values the kernel is using. Required to make sense from disassembled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * TLB exception handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void output_pgtable_bits_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define pr_define(fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pr_debug("#define " fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_debug("#include <asm/asm.h>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pr_debug("#include <asm/regdef.h>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef _PAGE_NO_EXEC_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (cpu_has_rixi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void dump_handler(const char *symbol, const void *start, const void *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int count = (end - start) / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) const u32 *handler = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pr_debug("LEAF(%s)\n", symbol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pr_debug("\t.set push\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pr_debug("\t.set noreorder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pr_debug("\t.set\tpop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pr_debug("\tEND(%s)\n", symbol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* The only general purpose registers allowed in TLB handlers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define K0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define K1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Some CP0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define C0_INDEX 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define C0_ENTRYLO0 2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define C0_TCBIND 2, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define C0_ENTRYLO1 3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define C0_CONTEXT 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define C0_PAGEMASK 5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define C0_PWBASE 5, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define C0_PWFIELD 5, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define C0_PWSIZE 5, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define C0_PWCTL 6, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define C0_BADVADDR 8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define C0_PGD 9, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define C0_ENTRYHI 10, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define C0_EPC 14, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define C0_XCONTEXT 20, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* The worst case length of the handler is around 18 instructions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Maximum space available is 32 instructions for R3000 and 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * instructions for R4000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * We deliberately chose a buffer size of 128, so we won't scribble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * over anything important on overflow before we panic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static u32 tlb_handler[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* simply assume worst case size for labels and relocs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct uasm_label labels[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct uasm_reloc relocs[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int check_for_high_segbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static bool fill_includes_sw_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static unsigned int kscratch_used_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline int __maybe_unused c0_kscratch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case CPU_XLP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case CPU_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int allocate_kscratch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) r = ffs(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (r == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) r--; /* make it zero based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) kscratch_used_mask |= (1 << r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int scratch_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int pgd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) EXPORT_SYMBOL_GPL(pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct work_registers build_get_work_registers(u32 **p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct work_registers r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (scratch_reg >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Save in CPU local C0_KScratch? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) r.r1 = K0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) r.r2 = K1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) r.r3 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (num_possible_cpus() > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Get smp_processor_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* handler_reg_save index in K0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) UASM_i_LA(p, K1, (long)&handler_reg_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) UASM_i_ADDU(p, K0, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) UASM_i_LA(p, K0, (long)&handler_reg_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* K0 now points to save area, save $1 and $2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) r.r1 = K1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) r.r2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) r.r3 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void build_restore_work_registers(u32 **p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (scratch_reg >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* K0 already points to save area, restore $1 and $2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * we cannot do r3000 under these circumstances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * The R3000 TLB handler is simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void build_r3000_tlb_refill_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) long pgdc = (long)pgd_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) memset(tlb_handler, 0, sizeof(tlb_handler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) p = tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) uasm_i_mfc0(&p, K0, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uasm_i_srl(&p, K0, K0, 22); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uasm_i_sll(&p, K0, K0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uasm_i_addu(&p, K1, K1, K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uasm_i_mfc0(&p, K0, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uasm_i_addu(&p, K1, K1, K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uasm_i_lw(&p, K0, 0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uasm_i_nop(&p); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) uasm_i_tlbwr(&p); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) uasm_i_jr(&p, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) uasm_i_rfe(&p); /* branch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (p > tlb_handler + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) panic("TLB refill handler space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_debug("Wrote TLB refill handler (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) (unsigned int)(p - tlb_handler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) memcpy((void *)ebase, tlb_handler, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) local_flush_icache_range(ebase, ebase + 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * The R4000 TLB handler is much more complicated. We have two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * consecutive handler areas with 32 instructions space each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Since they aren't used at the same time, we can overflow in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * other one.To keep things simple, we first assume linear space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * then we relocate it to the final handler layout as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static u32 final_handler[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Hazards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * 2. A timing hazard exists for the TLBP instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * stalling_instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * TLBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * The JTLB is being read for the TLBP throughout the stall generated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * previous instruction. This is not really correct as the stalling instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * can modify the address used to access the JTLB. The failure symptom is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * the TLBP instruction will use an address created for the stalling instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * and not the address held in C0_ENHI and thus report the wrong results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * The software work-around is to not allow the instruction preceding the TLBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * to stall - make it an NOP or some other instruction guaranteed not to stall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Errata 2 will not be fixed. This errata is also on the R5000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void __maybe_unused build_tlb_probe_entry(u32 **p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case CPU_R4600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case CPU_R4700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case CPU_R5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case CPU_NEVADA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) uasm_i_tlbp(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uasm_i_tlbp(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void build_tlb_write_entry(u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) enum tlb_write_entry wmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void(*tlbw)(u32 **) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) switch (wmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case tlb_random: tlbw = uasm_i_tlbwr; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case tlb_indexed: tlbw = uasm_i_tlbwi; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (cpu_has_mips_r2_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (cpu_has_mips_r2_exec_hazard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case CPU_R4000PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case CPU_R4000SC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case CPU_R4000MC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case CPU_R4400PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case CPU_R4400SC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case CPU_R4400MC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * This branch uses up a mtc0 hazard nop slot and saves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * two nops after the tlbw instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uasm_bgezl_hazard(p, r, hazard_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uasm_bgezl_label(l, p, hazard_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hazard_instance++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case CPU_R4600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case CPU_R4700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case CPU_R5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case CPU_NEVADA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uasm_i_nop(p); /* QED specifies 2 nops hazard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uasm_i_nop(p); /* QED specifies 2 nops hazard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case CPU_5KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case CPU_TX49XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case CPU_PR4450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case CPU_XLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case CPU_R10000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case CPU_R12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case CPU_R14000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case CPU_R16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case CPU_4KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case CPU_4KEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case CPU_M14KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case CPU_M14KEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case CPU_SB1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case CPU_SB1A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case CPU_4KSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case CPU_20KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case CPU_25KF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case CPU_BMIPS32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case CPU_BMIPS3300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case CPU_BMIPS4350:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case CPU_BMIPS4380:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case CPU_BMIPS5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case CPU_LOONGSON2EF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case CPU_LOONGSON64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case CPU_R5500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (m4kc_tlbp_war())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case CPU_ALCHEMY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case CPU_RM7000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case CPU_VR4181:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case CPU_VR4181A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case CPU_XBURST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tlbw(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) panic("No TLB refill handler yet (CPU type: %d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) current_cpu_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) EXPORT_SYMBOL_GPL(build_tlb_write_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (_PAGE_GLOBAL_SHIFT == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* pte_t is already in EntryLo format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (cpu_has_rixi && !!_PAGE_NO_EXEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (fill_includes_sw_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) UASM_i_ROTR(p, reg, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int tmp, enum label_id lid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int restore_scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (restore_scratch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Ensure the MFC0 below observes the value written to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * KScratch register by the prior MTC0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Reset default page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (PM_DEFAULT_MASK >> 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) uasm_i_mtc0(p, tmp, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else if (PM_DEFAULT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) uasm_i_mtc0(p, tmp, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) uasm_i_mtc0(p, 0, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) UASM_i_LW(p, 1, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Reset default page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (PM_DEFAULT_MASK >> 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) uasm_i_mtc0(p, tmp, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) } else if (PM_DEFAULT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uasm_i_mtc0(p, tmp, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uasm_il_b(p, r, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uasm_i_mtc0(p, 0, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) enum tlb_write_entry wmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int restore_scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Set huge page tlb entry size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) uasm_i_mtc0(p, tmp, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) build_tlb_write_entry(p, l, r, wmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Check if Huge PTE is present, if so then jump to LABEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned int pmd, int lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) UASM_i_LW(p, tmp, 0, pmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) uasm_il_bnez(p, r, tmp, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void build_huge_update_entries(u32 **p, unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned int tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int small_sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * A huge PTE describes an area the size of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * configured huge page size. This is twice the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * of the large TLB entry size we intend to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * A TLB entry half the size of the configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * huge page size is configured into entrylo0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * and entrylo1 to cover the contiguous huge PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* We can clobber tmp. It isn't used after this.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!small_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) build_convert_pte_to_entrylo(p, pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* convert to entrylo1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (small_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) UASM_i_ADDU(p, pte, pte, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unsigned int ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) UASM_i_SC(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uasm_il_beqz(p, r, pte, label_tlb_huge_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) UASM_i_SW(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (cpu_has_ftlb && flush) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) BUG_ON(!cpu_has_tlbinv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) UASM_i_MFC0(p, ptr, C0_ENTRYHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) UASM_i_MTC0(p, ptr, C0_ENTRYHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) build_tlb_write_entry(p, l, r, tlb_indexed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) UASM_i_MTC0(p, ptr, C0_ENTRYHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) build_huge_update_entries(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) build_huge_update_entries(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * TMP and PTR are scratch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * TMP will be clobbered, PTR will hold the pmd entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned int tmp, unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) long pgdc = (long)pgd_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * The vmalloc handling is not in the hotpath.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) uasm_i_dmfc0(p, tmp, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * The kernel currently implicitely assumes that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * MIPS SEGBITS parameter for the processor is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * allocate virtual addresses outside the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * that doesn't prevent user code from accessing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * higher xuseg addresses. Here, we make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * everything but the lower xuseg addresses goes down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * the module_alloc/vmalloc path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) uasm_il_bnez(p, r, ptr, label_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) uasm_il_bltz(p, r, tmp, label_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (pgd_reg != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* pgd is in pgd_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (cpu_has_ldpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) UASM_i_MFC0(p, ptr, C0_PWBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * &pgd << 11 stored in CONTEXT [23..63].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) UASM_i_MFC0(p, ptr, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Clear lower 23 bits of context. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uasm_i_dins(p, ptr, 0, 0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* 1 0 1 0 1 << 6 xkphys cached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) uasm_i_ori(p, ptr, ptr, 0x540);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) uasm_i_drotr(p, ptr, ptr, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #elif defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) UASM_i_LA_mostly(p, tmp, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) uasm_i_daddu(p, ptr, ptr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) uasm_i_dmfc0(p, tmp, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) UASM_i_LA_mostly(p, ptr, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) uasm_l_vmalloc_done(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* get pgd offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #ifndef __PAGETABLE_PUD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) EXPORT_SYMBOL_GPL(build_get_pmde64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * BVADDR is the faulting address, PTR is scratch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * PTR will hold the pgd for vmalloc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unsigned int bvaddr, unsigned int ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) enum vmalloc64_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) long swpd = (long)swapper_pg_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int single_insn_swpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int did_vmalloc_branch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) uasm_l_vmalloc(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (mode != not_refill && check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (single_insn_swpd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) did_vmalloc_branch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!did_vmalloc_branch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (single_insn_swpd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uasm_il_b(p, r, label_vmalloc_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) UASM_i_LA_mostly(p, ptr, swpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) uasm_il_b(p, r, label_vmalloc_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (uasm_in_compat_space_p(swpd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (mode != not_refill && check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) uasm_l_large_segbits_fault(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (mode == refill_scratch && scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * We get here if we are an xsseg address, or if we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * Ignoring xsseg (assume disabled so would generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * (address errors?), the only remaining possibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * is the upper xuseg addresses. On processors with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * addresses would have taken an address error. We try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * to mimic that here by taking a load/istream page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) uasm_i_sync(p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) uasm_i_jr(p, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (mode == refill_scratch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) UASM_i_LW(p, 1, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #else /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * TMP and PTR are scratch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * TMP will be clobbered, PTR will hold the pgd entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (pgd_reg != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* pgd is in pgd_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) long pgdc = (long)pgd_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) UASM_i_LA_mostly(p, tmp, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) uasm_i_addu(p, ptr, tmp, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) UASM_i_LA_mostly(p, ptr, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) EXPORT_SYMBOL_GPL(build_get_pgde32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #endif /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static void build_adjust_context(u32 **p, unsigned int ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case CPU_VR41XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case CPU_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case CPU_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case CPU_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) case CPU_VR4131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case CPU_VR4181:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case CPU_VR4181A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case CPU_VR4133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) shift += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) UASM_i_SRL(p, ctx, ctx, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) uasm_i_andi(p, ctx, ctx, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * Bug workaround for the Nevada. It seems as if under certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * circumstances the move from cp0_context might produce a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * bogus result when the mfc0 instruction and its consumer are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * in a different cacheline or a load instruction, probably any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * memory reference, is between them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case CPU_NEVADA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) UASM_i_LW(p, ptr, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GET_CONTEXT(p, tmp); /* get context reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GET_CONTEXT(p, tmp); /* get context reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) UASM_i_LW(p, ptr, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) build_adjust_context(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) EXPORT_SYMBOL_GPL(build_get_ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int pte_off_even = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int pte_off_odd = sizeof(pte_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* The low 32 bits of EntryLo is stored in pte_high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pte_off_even += offsetof(pte_t, pte_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) pte_off_odd += offsetof(pte_t, pte_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (IS_ENABLED(CONFIG_XPA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (cpu_has_xpa && !mips_xpa_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) uasm_i_lw(p, tmp, 0, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) uasm_i_ext(p, tmp, tmp, 0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (cpu_has_xpa && !mips_xpa_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) uasm_i_ext(p, tmp, tmp, 0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (r45k_bvahwbug())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) build_tlb_probe_entry(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) build_convert_pte_to_entrylo(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (r4k_250MHZhwbug())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) UASM_i_MTC0(p, 0, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) build_convert_pte_to_entrylo(p, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (r45k_bvahwbug())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) uasm_i_mfc0(p, tmp, C0_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (r4k_250MHZhwbug())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) UASM_i_MTC0(p, 0, C0_ENTRYLO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) EXPORT_SYMBOL_GPL(build_update_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct mips_huge_tlb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int huge_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int restore_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bool need_reload_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static struct mips_huge_tlb_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct uasm_reloc **r, unsigned int tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) unsigned int ptr, int c0_scratch_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct mips_huge_tlb_info rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unsigned int even, odd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int vmalloc_branch_delay_filled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) const int scratch = 1; /* Our extra working register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) rv.huge_pte = scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) rv.restore_scratch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rv.need_reload_pte = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) UASM_i_MFC0(p, tmp, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (pgd_reg != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) UASM_i_MFC0(p, ptr, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (c0_scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) uasm_i_dsrl_safe(p, scratch, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) uasm_il_bnez(p, r, scratch, label_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (pgd_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) vmalloc_branch_delay_filled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Clear lower 23 bits of context. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) uasm_i_dins(p, ptr, 0, 0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (pgd_reg != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) UASM_i_MFC0(p, ptr, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) UASM_i_MFC0(p, tmp, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (c0_scratch_reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (pgd_reg == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Clear lower 23 bits of context. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) uasm_i_dins(p, ptr, 0, 0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) uasm_il_bltz(p, r, tmp, label_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (pgd_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) vmalloc_branch_delay_filled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* 1 0 1 0 1 << 6 xkphys cached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) uasm_i_ori(p, ptr, ptr, 0x540);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) uasm_i_drotr(p, ptr, ptr, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #ifdef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define LOC_PTEP scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define LOC_PTEP ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!vmalloc_branch_delay_filled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* get pgd offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) uasm_l_vmalloc_done(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * tmp ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * fall-through case = badvaddr *pgd_current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * vmalloc case = badvaddr swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (vmalloc_branch_delay_filled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* get pgd offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #ifdef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GET_CONTEXT(p, tmp); /* get context reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (use_lwx_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #ifndef __PAGETABLE_PUD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* get pud offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (use_lwx_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) UASM_i_LWX(p, ptr, scratch, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) UASM_i_LW(p, ptr, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* ptr contains a pointer to PMD entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* tmp contains the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* get pmd offset in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GET_CONTEXT(p, tmp); /* get context reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (use_lwx_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) UASM_i_LWX(p, scratch, scratch, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) UASM_i_LW(p, scratch, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Adjust the context during the load latency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) build_adjust_context(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * The in the LWX case we don't want to do the load in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * delay slot. It cannot issue in the same cycle and may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * speculative and unneeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (use_lwx_insns())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* build_update_entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (use_lwx_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) even = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) odd = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) UASM_i_LWX(p, even, scratch, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) UASM_i_LWX(p, odd, scratch, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) even = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) odd = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) UASM_i_LW(p, even, 0, ptr); /* get even pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (cpu_has_rixi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (c0_scratch_reg >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) build_tlb_write_entry(p, l, r, tlb_random);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) uasm_l_leave(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) rv.restore_scratch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) build_tlb_write_entry(p, l, r, tlb_random);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) uasm_l_leave(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) build_tlb_write_entry(p, l, r, tlb_random);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) uasm_l_leave(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) rv.restore_scratch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) uasm_i_eret(p); /* return from trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * because EXL == 0. If we wrap, we can also use the 32 instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * slots before the XTLB refill exception handler which belong to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * unused TLB refill exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define MIPS64_REFILL_INSNS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static void build_r4000_tlb_refill_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 *p = tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) unsigned int final_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct mips_huge_tlb_info htlb_info __maybe_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) enum vmalloc64_mode vmalloc_mode __maybe_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) memset(tlb_handler, 0, sizeof(tlb_handler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) memset(final_handler, 0, sizeof(final_handler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) scratch_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) vmalloc_mode = refill_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) htlb_info.huge_pte = K0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) htlb_info.restore_scratch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) htlb_info.need_reload_pte = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) vmalloc_mode = refill_noscratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * create the plain linear handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (bcm1250_m3_war()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) unsigned int segbits = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) uasm_i_dmfc0(&p, K0, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) uasm_i_xor(&p, K0, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) uasm_i_dsrl_safe(&p, K1, K0, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) uasm_i_or(&p, K0, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) uasm_il_bnez(&p, &r, K0, label_leave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* No need for uasm_i_nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) build_get_ptep(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) build_update_entries(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) build_tlb_write_entry(&p, &l, &r, tlb_random);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) uasm_l_leave(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) uasm_i_eret(&p); /* return from trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) uasm_l_tlb_huge_update(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (htlb_info.need_reload_pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) build_huge_update_entries(&p, htlb_info.huge_pte, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) htlb_info.restore_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * Overflow check: For the 64bit handler, we need at least one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * free instruction slot for the wrap-around branch. In worst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * case, if the intended insertion point is a delay slot, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * need three, with the second nop'ed and the third being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) switch (boot_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (sizeof(long) == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) case CPU_LOONGSON2EF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Loongson2 ebase is different than r4k, we have more space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if ((p - tlb_handler) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) panic("TLB refill handler space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * Now fold the handler in the TLB refill handler space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) f = final_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* Simplest case, just copy the handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) uasm_copy_handler(relocs, labels, tlb_handler, p, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) final_len = p - tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) && uasm_insn_has_bdelay(relocs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) tlb_handler + MIPS64_REFILL_INSNS - 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) panic("TLB refill handler space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * Now fold the handler in the TLB refill handler space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) f = final_handler + MIPS64_REFILL_INSNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* Just copy the handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) uasm_copy_handler(relocs, labels, tlb_handler, p, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) final_len = p - tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) const enum label_id ls = label_tlb_huge_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) const enum label_id ls = label_vmalloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u32 *split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int ov = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) BUG_ON(i == ARRAY_SIZE(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) split = labels[i].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * See if we have overflown one way or the other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (split > tlb_handler + MIPS64_REFILL_INSNS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) split < p - MIPS64_REFILL_INSNS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ov = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (ov) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * Split two instructions before the end. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * for the branch and one for the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * in the delay slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) split = tlb_handler + MIPS64_REFILL_INSNS - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * If the branch would fall in a delay slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * we must back up an additional instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * so that it is no longer in a delay slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (uasm_insn_has_bdelay(relocs, split - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) split--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Copy first part of the handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) uasm_copy_handler(relocs, labels, tlb_handler, split, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) f += split - tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (ov) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Insert branch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) uasm_l_split(&l, final_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) uasm_il_b(&f, &r, label_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (uasm_insn_has_bdelay(relocs, split))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) uasm_i_nop(&f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) uasm_copy_handler(relocs, labels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) split, split + 1, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) uasm_move_labels(labels, f, f + 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) f++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) split++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Copy the rest of the handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) uasm_copy_handler(relocs, labels, split, p, final_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) (p - split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) pr_debug("Wrote TLB refill handler (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) final_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) memcpy((void *)ebase, final_handler, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) local_flush_icache_range(ebase, ebase + 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static void setup_pw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) unsigned int pwctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) unsigned long pgd_i, pgd_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) unsigned long pmd_i, pmd_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) unsigned long pt_i, pt_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) unsigned long pte_i, pte_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) unsigned long psn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pgd_i = PGDIR_SHIFT; /* 1st level PGD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pmd_i = PMD_SHIFT; /* 2nd level PMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pmd_w = PMD_SHIFT - PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) pt_i = PAGE_SHIFT; /* 3rd level PTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pt_w = PAGE_SHIFT - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) pte_i = ilog2(_PAGE_GLOBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pte_w = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pwctl = 1 << 30; /* Set PWDirExt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) pwctl |= (1 << 6 | psn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) write_c0_pwctl(pwctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) write_c0_kpgd((long)swapper_pg_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static void build_loongson3_tlb_refill_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u32 *p = tlb_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) memset(tlb_handler, 0, sizeof(tlb_handler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) uasm_i_dmfc0(&p, K0, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) uasm_il_beqz(&p, &r, K1, label_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) uasm_l_vmalloc(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) uasm_i_dmfc0(&p, K1, C0_PGD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) uasm_i_ldpte(&p, K1, 0); /* even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) uasm_i_ldpte(&p, K1, 1); /* odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) uasm_i_tlbwr(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* restore page mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (PM_DEFAULT_MASK >> 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) uasm_i_mtc0(&p, K0, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) } else if (PM_DEFAULT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) uasm_i_mtc0(&p, K0, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) uasm_i_mtc0(&p, 0, C0_PAGEMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) uasm_i_eret(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (check_for_high_segbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) uasm_l_large_segbits_fault(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) uasm_i_jr(&p, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) local_flush_icache_range(ebase + 0x80, ebase + 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dump_handler("loongson3_tlb_refill",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void build_setup_pgd(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) const int a0 = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) const int __maybe_unused a1 = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) const int __maybe_unused a2 = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) long pgdc = (long)pgd_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pgd_reg = allocate_kscratch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (pgd_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* PGD << 11 in c0_Context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * If it is a ckseg0 address, convert to a physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * address. Shifting right by 29 and adding 4 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * result in zero for these addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) UASM_i_SRA(&p, a1, a0, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) UASM_i_ADDIU(&p, a1, a1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) uasm_l_tlbl_goaround1(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) UASM_i_SLL(&p, a0, a0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) UASM_i_MTC0(&p, a0, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) uasm_i_jr(&p, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* PGD in c0_KScratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (cpu_has_ldpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) UASM_i_MTC0(&p, a0, C0_PWBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) uasm_i_jr(&p, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* Save PGD to pgd_current[smp_processor_id()] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) UASM_i_LA_mostly(&p, a2, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) UASM_i_ADDU(&p, a2, a2, a1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) UASM_i_LA_mostly(&p, a2, pgdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #endif /* SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* if pgd_reg is allocated, save PGD also to scratch register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (pgd_reg != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) uasm_i_jr(&p, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) uasm_i_jr(&p, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (p >= (u32 *)tlbmiss_handler_setup_pgd_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) panic("tlbmiss_handler_setup_pgd space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) tlbmiss_handler_setup_pgd_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) uasm_i_sync(p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (cpu_has_64bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) uasm_i_lld(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) UASM_i_LL(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (cpu_has_64bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) uasm_i_ld(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) UASM_i_LW(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) unsigned int mode, unsigned int scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) unsigned int swmode = mode & ~hwmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) uasm_i_lui(p, scratch, swmode >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) uasm_i_or(p, pte, pte, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) BUG_ON(swmode & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) uasm_i_ori(p, pte, pte, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (cpu_has_64bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) uasm_i_scd(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) UASM_i_SC(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (r10000_llsc_war())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (!cpu_has_64bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* no uasm_i_nop needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) uasm_i_ori(p, pte, pte, hwmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) BUG_ON(hwmode & ~0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* no uasm_i_nop needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) uasm_i_lw(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) # else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (cpu_has_64bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) uasm_i_sd(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) UASM_i_SW(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) # ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (!cpu_has_64bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) uasm_i_ori(p, pte, pte, hwmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) BUG_ON(hwmode & ~0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) uasm_i_lw(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * Check if PTE is present, if not then jump to LABEL. PTR points to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * the page table where this PTE is located, PTE will be re-loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * with it's original value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) build_pte_present(u32 **p, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) int pte, int ptr, int scratch, enum label_id lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) int t = scratch >= 0 ? scratch : pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) int cur = pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (cpu_has_rixi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (_PAGE_PRESENT_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) cur = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) uasm_i_andi(p, t, cur, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) uasm_il_beqz(p, r, t, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (pte == t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* You lose the SMP race :-(*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) iPTE_LW(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (_PAGE_PRESENT_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) cur = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) uasm_i_andi(p, t, cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) uasm_il_bnez(p, r, t, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (pte == t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* You lose the SMP race :-(*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) iPTE_LW(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* Make PTE valid, store result in PTR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) unsigned int ptr, unsigned int scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) iPTE_SW(p, r, pte, ptr, mode, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * Check if PTE can be written to, if not branch to LABEL. Regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * restore PTE with value from PTR when done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) build_pte_writable(u32 **p, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) unsigned int pte, unsigned int ptr, int scratch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) enum label_id lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) int t = scratch >= 0 ? scratch : pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) int cur = pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (_PAGE_PRESENT_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) cur = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) uasm_i_andi(p, t, cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) uasm_i_xori(p, t, t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) uasm_il_bnez(p, r, t, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (pte == t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* You lose the SMP race :-(*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) iPTE_LW(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* Make PTE writable, update software status bits as well, then store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * at PTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) unsigned int ptr, unsigned int scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) | _PAGE_DIRTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) iPTE_SW(p, r, pte, ptr, mode, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * Check if PTE can be modified, if not branch to LABEL. Regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * restore PTE with value from PTR when done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) build_pte_modifiable(u32 **p, struct uasm_reloc **r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) unsigned int pte, unsigned int ptr, int scratch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) enum label_id lid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) int t = scratch >= 0 ? scratch : pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) uasm_i_andi(p, t, t, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) uasm_il_beqz(p, r, t, lid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (pte == t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* You lose the SMP race :-(*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) iPTE_LW(p, pte, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * R3000 style TLB load/store/modify handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * This places the pte into ENTRYLO0 and writes it with tlbwi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * Then it returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) uasm_i_tlbwi(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) uasm_i_jr(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) uasm_i_rfe(p); /* branch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * This places the pte into ENTRYLO0 and writes it with tlbwi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * or tlbwr as appropriate. This is because the index register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * may have the probe fail bit set as a result of a trap on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * kseg2 access, i.e. without refill. Then it returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct uasm_reloc **r, unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) unsigned int tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) uasm_i_mfc0(p, tmp, C0_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) uasm_i_tlbwi(p); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) uasm_i_jr(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) uasm_i_rfe(p); /* branch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) uasm_l_r3000_write_probe_fail(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) uasm_i_tlbwr(p); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) uasm_i_jr(p, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) uasm_i_rfe(p); /* branch delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) long pgdc = (long)pgd_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) uasm_i_mfc0(p, pte, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) uasm_i_srl(p, pte, pte, 22); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) uasm_i_sll(p, pte, pte, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) uasm_i_addu(p, ptr, ptr, pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) uasm_i_mfc0(p, pte, C0_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) uasm_i_addu(p, ptr, ptr, pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) uasm_i_lw(p, pte, 0, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) uasm_i_tlbp(p); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static void build_r3000_tlb_load_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) u32 *p = (u32 *)handle_tlbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) memset(p, 0, handle_tlbl_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) build_r3000_tlbchange_handler_head(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) uasm_i_nop(&p); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) build_make_valid(&p, &r, K0, K1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) uasm_l_nopage_tlbl(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (p >= (u32 *)handle_tlbl_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) panic("TLB load handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) (unsigned int)(p - (u32 *)handle_tlbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static void build_r3000_tlb_store_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) u32 *p = (u32 *)handle_tlbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) memset(p, 0, handle_tlbs_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) build_r3000_tlbchange_handler_head(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) uasm_i_nop(&p); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) build_make_write(&p, &r, K0, K1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) uasm_l_nopage_tlbs(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (p >= (u32 *)handle_tlbs_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) panic("TLB store handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) (unsigned int)(p - (u32 *)handle_tlbs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static void build_r3000_tlb_modify_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) u32 *p = (u32 *)handle_tlbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) memset(p, 0, handle_tlbm_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) build_r3000_tlbchange_handler_head(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) uasm_i_nop(&p); /* load delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) build_make_write(&p, &r, K0, K1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) build_r3000_pte_reload_tlbwi(&p, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) uasm_l_nopage_tlbm(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (p >= (u32 *)handle_tlbm_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) panic("TLB modify handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) (unsigned int)(p - (u32 *)handle_tlbm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static bool cpu_has_tlbex_tlbp_race(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * When a Hardware Table Walker is running it can replace TLB entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * at any time, leading to a race between it & the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (cpu_has_htw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * If the CPU shares FTLB RAM with its siblings then our entry may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * replaced at any time by a sibling performing a write to the FTLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (cpu_has_shared_ftlb_ram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* In all other cases there ought to be no race condition to handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * R4000 style TLB load/store/modify handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static struct work_registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct uasm_reloc **r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct work_registers wr = build_get_work_registers(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * For huge tlb entries, pmd doesn't contain an address but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * instead contains the tlb pte. Check the PAGE_HUGE bit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * see if we need to jump to huge tlb processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) UASM_i_LW(p, wr.r2, 0, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) uasm_l_smp_pgtable_change(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (!m4kc_tlbp_war()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) build_tlb_probe_entry(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (cpu_has_tlbex_tlbp_race()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* race condition happens, leaving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) uasm_i_ehb(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) uasm_i_mfc0(p, wr.r3, C0_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) uasm_il_bltz(p, r, wr.r3, label_leave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) uasm_i_nop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) return wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct uasm_reloc **r, unsigned int tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) unsigned int ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) build_update_entries(p, tmp, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) build_tlb_write_entry(p, l, r, tlb_indexed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) uasm_l_leave(l, *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) build_restore_work_registers(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) uasm_i_eret(p); /* return from trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static void build_r4000_tlb_load_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct work_registers wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) memset(p, 0, handle_tlbl_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) if (bcm1250_m3_war()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) unsigned int segbits = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) uasm_i_dmfc0(&p, K0, C0_BADVADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) uasm_i_xor(&p, K0, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) uasm_i_dsrl_safe(&p, K1, K0, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) uasm_i_or(&p, K0, K0, K1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) uasm_il_bnez(&p, &r, K0, label_leave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* No need for uasm_i_nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (m4kc_tlbp_war())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (cpu_has_rixi && !cpu_has_rixiex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * If the page is not _PAGE_VALID, RI or XI could not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * have triggered it. Skip the expensive test..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) label_tlbl_goaround1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) * Warn if something may race with us & replace the TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * before we read it here. Everything with such races should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * also have dedicated RiXi exception handlers, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * shouldn't be hit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) uasm_i_tlbr(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (cpu_has_mips_r2_exec_hazard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) case CPU_CAVIUM_OCTEON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) case CPU_CAVIUM_OCTEON_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) case CPU_CAVIUM_OCTEON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* Examine entrylo 0 or 1 based on ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) uasm_i_beqz(&p, wr.r3, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* load it in the delay slot*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /* load it if ptr is odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) * If the entryLo (now in wr.r3) is valid (bit 1), RI or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * XI must have triggered it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) uasm_l_tlbl_goaround1(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) uasm_i_andi(&p, wr.r3, wr.r3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) uasm_l_tlbl_goaround1(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) * This is the entry point when build_r4000_tlbchange_handler_head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * spots a huge page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) uasm_l_tlb_huge_update(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) iPTE_LW(&p, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (cpu_has_rixi && !cpu_has_rixiex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * If the page is not _PAGE_VALID, RI or XI could not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) * have triggered it. Skip the expensive test..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) label_tlbl_goaround2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * Warn if something may race with us & replace the TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * before we read it here. Everything with such races should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * also have dedicated RiXi exception handlers, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * shouldn't be hit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) uasm_i_tlbr(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (cpu_has_mips_r2_exec_hazard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) case CPU_CAVIUM_OCTEON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) case CPU_CAVIUM_OCTEON_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) case CPU_CAVIUM_OCTEON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* Examine entrylo 0 or 1 based on ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) uasm_i_beqz(&p, wr.r3, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /* load it in the delay slot*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* load it if ptr is odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * If the entryLo (now in wr.r3) is valid (bit 1), RI or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * XI must have triggered it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (use_bbit_insns()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) uasm_i_andi(&p, wr.r3, wr.r3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (PM_DEFAULT_MASK == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * We clobbered C0_PAGEMASK, restore it. On the other branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * it is restored in build_huge_tlb_write_entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) uasm_l_tlbl_goaround2(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) uasm_l_nopage_tlbl(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) uasm_i_sync(&p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) build_restore_work_registers(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #ifdef CONFIG_CPU_MICROMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if ((unsigned long)tlb_do_page_fault_0 & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) uasm_i_jr(&p, K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (p >= (u32 *)handle_tlbl_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) panic("TLB load handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) (unsigned int)(p - (u32 *)handle_tlbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static void build_r4000_tlb_store_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) struct work_registers wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) memset(p, 0, handle_tlbs_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if (m4kc_tlbp_war())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * This is the entry point when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * build_r4000_tlbchange_handler_head spots a huge page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) uasm_l_tlb_huge_update(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) iPTE_LW(&p, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) uasm_i_ori(&p, wr.r1, wr.r1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) uasm_l_nopage_tlbs(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) uasm_i_sync(&p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) build_restore_work_registers(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #ifdef CONFIG_CPU_MICROMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if ((unsigned long)tlb_do_page_fault_1 & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) uasm_i_jr(&p, K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (p >= (u32 *)handle_tlbs_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) panic("TLB store handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) (unsigned int)(p - (u32 *)handle_tlbs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static void build_r4000_tlb_modify_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) struct work_registers wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) memset(p, 0, handle_tlbm_end - (char *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (m4kc_tlbp_war())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* Present and writable bits set, set accessed and dirty bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * This is the entry point when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * build_r4000_tlbchange_handler_head spots a huge page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) uasm_l_tlb_huge_update(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) iPTE_LW(&p, wr.r1, wr.r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) build_tlb_probe_entry(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) uasm_i_ori(&p, wr.r1, wr.r1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) uasm_l_nopage_tlbm(&l, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) uasm_i_sync(&p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) build_restore_work_registers(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) #ifdef CONFIG_CPU_MICROMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if ((unsigned long)tlb_do_page_fault_1 & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) uasm_i_jr(&p, K0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if (p >= (u32 *)handle_tlbm_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) panic("TLB modify handler fastpath space exceeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) (unsigned int)(p - (u32 *)handle_tlbm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static void flush_tlb_handlers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) local_flush_icache_range((unsigned long)handle_tlbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) (unsigned long)handle_tlbl_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) local_flush_icache_range((unsigned long)handle_tlbs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) (unsigned long)handle_tlbs_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) local_flush_icache_range((unsigned long)handle_tlbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) (unsigned long)handle_tlbm_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) (unsigned long)tlbmiss_handler_setup_pgd_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static void print_htw_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) unsigned int pwctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) const int field = 2 * sizeof(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) config = read_c0_pwfield();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) field, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) config = read_c0_pwsize();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) field, config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) pwctl = read_c0_pwctl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) pwctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) static void config_htw_params(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) unsigned long pwfield, pwsize, ptei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * We are using 2-level page tables, so we only need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * setup GDW and PTW appropriately. UDW and MDW will remain 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * write values less than 0xc in these fields because the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * write will be dropped. As a result of which, we must preserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * the original reset values and overwrite only what we really want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) pwfield = read_c0_pwfield();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* re-initialize the GDI field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) pwfield &= ~MIPS_PWFIELD_GDI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) /* re-initialize the PTI field including the even/odd bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pwfield &= ~MIPS_PWFIELD_PTI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (CONFIG_PGTABLE_LEVELS >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) pwfield &= ~MIPS_PWFIELD_MDI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) /* Set the PTEI right shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) pwfield |= ptei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) write_c0_pwfield(pwfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) /* Check whether the PTEI value is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) pwfield = read_c0_pwfield();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) != ptei) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ptei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) * Drop option to avoid HTW being enabled via another path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) * (eg htw_reset())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) current_cpu_data.options &= ~MIPS_CPU_HTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (CONFIG_PGTABLE_LEVELS >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /* Set pointer size to size of directory pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) if (IS_ENABLED(CONFIG_64BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) pwsize |= MIPS_PWSIZE_PS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) /* PTEs may be multiple pointers long (e.g. with XPA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) & MIPS_PWSIZE_PTEW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) write_c0_pwsize(pwsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* Make sure everything is set before we enable the HTW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) * the pwctl fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) config = 1 << MIPS_PWCTL_PWEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if (IS_ENABLED(CONFIG_64BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) config |= MIPS_PWCTL_XU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) write_c0_pwctl(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) pr_info("Hardware Page Table Walker enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) print_htw_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) static void config_xpa_params(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #ifdef CONFIG_XPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) unsigned int pagegrain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (mips_xpa_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) pr_info("Extended Physical Addressing (XPA) disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) pagegrain = read_c0_pagegrain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) write_c0_pagegrain(pagegrain | PG_ELPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) pagegrain = read_c0_pagegrain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) if (pagegrain & PG_ELPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) pr_info("Extended Physical Addressing (XPA) enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) panic("Extended Physical Addressing (XPA) disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static void check_pabits(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) unsigned long entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) unsigned pabits, fillbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) * We'll only be making use of the fact that we can rotate bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) * into the fill if the CPU supports RIXI, so don't bother
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * probing this for CPUs which don't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) write_c0_entrylo0(~0ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) entry = read_c0_entrylo0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) /* clear all non-PFN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* find a lower bound on PABITS, and upper bound on fill bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) pabits = fls_long(entry) + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) /* minus the RI & XI bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) fillbits -= min_t(unsigned, fillbits, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (fillbits >= ilog2(_PAGE_NO_EXEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) fill_includes_sw_bits = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) pr_debug("Entry* registers contain %u fill bits\n", fillbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) void build_tlb_refill_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) * The refill handler is generated per-CPU, multi-node systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) * may have local storage for it. The other handlers are only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * needed once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static int run_once = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) panic("Kernels supporting XPA currently require CPUs with RIXI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) output_pgtable_bits_defines();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) check_pabits();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (cpu_has_3kex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (!run_once) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) build_setup_pgd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) build_r3000_tlb_refill_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) build_r3000_tlb_load_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) build_r3000_tlb_store_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) build_r3000_tlb_modify_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) flush_tlb_handlers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) run_once++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) panic("No R3000 TLB refill handler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (cpu_has_ldpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) setup_pw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (!run_once) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) scratch_reg = allocate_kscratch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) build_setup_pgd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) build_r4000_tlb_load_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) build_r4000_tlb_store_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) build_r4000_tlb_modify_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (cpu_has_ldpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) build_loongson3_tlb_refill_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) build_r4000_tlb_refill_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) flush_tlb_handlers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) run_once++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (cpu_has_xpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) config_xpa_params();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (cpu_has_htw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) config_htw_params();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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