Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * r2300.c: R2000 and R3000 specific mmu/cache code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * with a lot of changes to make this thing work for R3000s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Tx39XX R4k style caches added. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2002  Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2002  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/tlbmisc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/isadep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #undef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) extern void build_tlb_refill_handler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* CP0 hazard avoidance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define BARRIER				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	__asm__ __volatile__(		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		".set	push\n\t"	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		".set	noreorder\n\t"	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		"nop\n\t"		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		".set	pop\n\t")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) int r3k_have_wired_reg;			/* Should be in cpu_data? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* TLB operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void local_flush_tlb_from(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned long old_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	old_ctx = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	write_c0_entrylo0(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	while (entry < current_cpu_data.tlbsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		write_c0_index(entry << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		write_c0_entryhi((entry | 0x80000) << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		entry++;				/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	write_c0_entryhi(old_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) void local_flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	printk("[tlball]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	local_flush_tlb_from(r3k_have_wired_reg ? read_c0_wired() : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			   unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long asid_mask = cpu_asid_mask(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct mm_struct *mm = vma->vm_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (cpu_context(cpu, mm) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		unsigned long size, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			cpu_context(cpu, mm) & asid_mask, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (size <= current_cpu_data.tlbsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			int oldpid = read_c0_entryhi() & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			int newpid = cpu_context(cpu, mm) & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			start &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			end += PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			end &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				write_c0_entryhi(start | newpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				start += PAGE_SIZE;	/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				tlb_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				idx = read_c0_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				write_c0_entrylo0(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				write_c0_entryhi(KSEG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				if (idx < 0)		/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			write_c0_entryhi(oldpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			drop_mmu_context(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long size, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (size <= current_cpu_data.tlbsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		int pid = read_c0_entryhi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		start &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		end += PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		end &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			write_c0_entryhi(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			start += PAGE_SIZE;		/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			tlb_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			idx = read_c0_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			write_c0_entrylo0(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			write_c0_entryhi(KSEG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			if (idx < 0)			/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		write_c0_entryhi(pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned long asid_mask = cpu_asid_mask(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (cpu_context(cpu, vma->vm_mm) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		int oldpid, newpid, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		newpid = cpu_context(cpu, vma->vm_mm) & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		page &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		oldpid = read_c0_entryhi() & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		write_c0_entryhi(page | newpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		BARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		tlb_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		idx = read_c0_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		write_c0_entrylo0(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		write_c0_entryhi(KSEG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (idx < 0)				/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		write_c0_entryhi(oldpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned long asid_mask = cpu_asid_mask(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int idx, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * Handle debugger faulting in for debugee.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (current->active_mm != vma->vm_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pid = read_c0_entryhi() & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if ((pid != (cpu_context(cpu, vma->vm_mm) & asid_mask)) || (cpu_context(cpu, vma->vm_mm) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		       (cpu_context(cpu, vma->vm_mm)), pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	address &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	write_c0_entryhi(address | pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	BARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	tlb_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	idx = read_c0_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	write_c0_entrylo0(pte_val(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	write_c0_entryhi(address | pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (idx < 0) {					/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		tlb_write_random();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	write_c0_entryhi(pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		     unsigned long entryhi, unsigned long pagemask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned long asid_mask = cpu_asid_mask(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned long old_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	static unsigned long wired = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (r3k_have_wired_reg) {			/* TX39XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		unsigned long old_pagemask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		unsigned long w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		       entrylo0, entryhi, pagemask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		/* Save old context and create impossible VPN2 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		old_ctx = read_c0_entryhi() & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		old_pagemask = read_c0_pagemask();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		w = read_c0_wired();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		write_c0_wired(w + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		write_c0_index(w << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		write_c0_pagemask(pagemask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		write_c0_entryhi(entryhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		write_c0_entrylo0(entrylo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		BARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		write_c0_entryhi(old_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		write_c0_pagemask(old_pagemask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	} else if (wired < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifdef DEBUG_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		       entrylo0, entryhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		old_ctx = read_c0_entryhi() & asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		write_c0_entrylo0(entrylo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		write_c0_entryhi(entryhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		write_c0_index(wired);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		wired++;				/* BARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		tlb_write_indexed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		write_c0_entryhi(old_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void tlb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	case CPU_TX3922:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case CPU_TX3927:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		r3k_have_wired_reg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		write_c0_wired(0);		/* Set to 8 on reset... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	local_flush_tlb_from(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	build_tlb_refill_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }