^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc-rm7k.c: RM7000 cache management functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/bcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cacheflush.h> /* for run_uncached() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Primary cache parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define sc_lsize 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define tc_pagesize (32*128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Secondary cache parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Tertiary cache parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define tc_lsize 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) extern unsigned long icache_way_size, dcache_way_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static unsigned long tcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int rm7k_tcache_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Writeback and invalidate the primary cache dcache before DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * (XXX These need to be fixed ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long end, a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Catch bad driver code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) BUG_ON(size == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) blast_scache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!rm7k_tcache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) a = addr & ~(tc_pagesize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) end = (addr + size - 1) & ~(tc_pagesize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) while(1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) invalidate_tcache_page(a); /* Page_Invalidate_T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (a == end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) a += tc_pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void rm7k_sc_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long end, a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Catch bad driver code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BUG_ON(size == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) blast_inv_scache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!rm7k_tcache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) a = addr & ~(tc_pagesize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) end = (addr + size - 1) & ~(tc_pagesize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) while(1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) invalidate_tcache_page(a); /* Page_Invalidate_T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (a == end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) a += tc_pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void blast_rm7k_tcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long start = CKSEG0ADDR(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long end = start + tcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) write_c0_taglo(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cache_op(Page_Invalidate_T, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) start += tc_pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * This function is executed in uncached address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void __rm7k_tc_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) set_c0_config(RM7K_CONF_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) write_c0_taglo(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) write_c0_taghi(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < tcache_size; i += tc_lsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void rm7k_tc_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (read_c0_config() & RM7K_CONF_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) BUG_ON(tcache_size == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) run_uncached(__rm7k_tc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * This function is executed in uncached address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void __rm7k_sc_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) set_c0_config(RM7K_CONF_SE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) write_c0_taglo(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) write_c0_taghi(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) for (i = 0; i < scache_size; i += sc_lsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void rm7k_sc_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (read_c0_config() & RM7K_CONF_SE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_info("Enabling secondary cache...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) run_uncached(__rm7k_sc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (rm7k_tcache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rm7k_tc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void rm7k_tc_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) blast_rm7k_tcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clear_c0_config(RM7K_CONF_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void rm7k_sc_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clear_c0_config(RM7K_CONF_SE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (rm7k_tcache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rm7k_tc_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct bcache_ops rm7k_sc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .bc_enable = rm7k_sc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .bc_disable = rm7k_sc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .bc_wback_inv = rm7k_sc_wback_inv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .bc_inv = rm7k_sc_inv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * This is a probing function like the one found in c-r4k.c, we look for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * wrap around point with different addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void __probe_tcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long flags, addr, begin, end, pow2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) begin = (unsigned long) &_stext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) begin &= ~((8 * 1024 * 1024) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) end = begin + (8 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) set_c0_config(RM7K_CONF_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Fill size-multiple lines with a valid tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pow2 = (256 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (addr = begin; addr <= end; addr = (begin + pow2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long *p = (unsigned long *) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __asm__ __volatile__("nop" : : "r" (*p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pow2 <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Load first line with a 0 tag, to check after */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) write_c0_taglo(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) write_c0_taghi(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cache_op(Index_Store_Tag_T, begin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Look for the wrap-around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pow2 = (512 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cache_op(Index_Load_Tag_T, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!read_c0_taglo())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pow2 <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) addr -= begin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tcache_size = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clear_c0_config(RM7K_CONF_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void rm7k_sc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct cpuinfo_mips *c = ¤t_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int config = read_c0_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if ((config & RM7K_CONF_SC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c->scache.linesz = sc_lsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) c->scache.ways = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) c->scache.waybit= __ffs(scache_size / c->scache.ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) c->scache.waysize = scache_size / c->scache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (scache_size >> 10), sc_lsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!(config & RM7K_CONF_SE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rm7k_sc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bcops = &rm7k_sc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * While we're at it let's deal with the tertiary cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rm7k_tcache_init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tcache_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (config & RM7K_CONF_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * No efficient way to ask the hardware for the size of the tcache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * so must probe for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) run_uncached(__probe_tcache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rm7k_tc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) rm7k_tcache_init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) c->tcache.linesz = tc_lsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) c->tcache.ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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