Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2006 Chris Dearman (chris@mips.com),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/bcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * MIPS32/MIPS64 L2 cache handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Writeback and invalidate the secondary cache before DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	blast_scache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * Invalidate the secondary cache before DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static void mips_sc_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	unsigned long lsize = cpu_scache_line_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned long almask = ~(lsize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	cache_op(Hit_Writeback_Inv_SD, addr & almask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	blast_inv_scache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void mips_sc_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* L2 cache is permanently enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void mips_sc_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* L2 cache is permanently enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void mips_sc_prefetch_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long pftctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (mips_cm_revision() < CM_REV_CM2_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * If there is one or more L2 prefetch unit present then enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * prefetching for both code & data, for all ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	pftctl = read_gcr_l2_pft_control();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		write_gcr_l2_pft_control(pftctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					 CM_GCR_L2_PFT_CONTROL_B_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void mips_sc_prefetch_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (mips_cm_revision() < CM_REV_CM2_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				   CM_GCR_L2_PFT_CONTROL_B_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static bool mips_sc_prefetch_is_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned long pftctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (mips_cm_revision() < CM_REV_CM2_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	pftctl = read_gcr_l2_pft_control();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct bcache_ops mips_sc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.bc_enable = mips_sc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.bc_disable = mips_sc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.bc_wback_inv = mips_sc_wback_inv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.bc_inv = mips_sc_inv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.bc_prefetch_enable = mips_sc_prefetch_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.bc_prefetch_disable = mips_sc_prefetch_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.bc_prefetch_is_enabled = mips_sc_prefetch_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * Check if the L2 cache controller is activated on a particular platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * cache being disabled.  However there is no guarantee for this to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * true on all platforms.  In an act of stupidity the spec defined bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * 12..15 as implementation defined so below function will eventually have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * to be replaced by a platform specific probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int config2 = read_c0_config2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Check the bypass bit (L2B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case CPU_34K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case CPU_74K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case CPU_1004K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case CPU_1074K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case CPU_INTERAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case CPU_BMIPS5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	case CPU_QEMU_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case CPU_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (config2 & (1 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	tmp = (config2 >> 4) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (0 < tmp && tmp <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		c->scache.linesz = 2 << tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mips_sc_probe_cm3(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct cpuinfo_mips *c = &current_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned long cfg = read_gcr_l2_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long sets, line_sz, assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (cfg & CM_GCR_L2_CONFIG_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (sets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		c->scache.sets = 64 << sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	line_sz >>= __ffs(CM_GCR_L2_CONFIG_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (line_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		c->scache.linesz = 2 << line_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	assoc = cfg & CM_GCR_L2_CONFIG_ASSOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	assoc >>= __ffs(CM_GCR_L2_CONFIG_ASSOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	c->scache.ways = assoc + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	c->scache.waysize = c->scache.sets * c->scache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	c->scache.waybit = __ffs(c->scache.waysize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (c->scache.linesz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		c->options |= MIPS_CPU_INCLUSIVE_CACHES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline int mips_sc_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct cpuinfo_mips *c = &current_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	unsigned int config1, config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Mark as not present until probe completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (mips_cm_revision() >= CM_REV_CM3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return mips_sc_probe_cm3();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Ignore anything but MIPSxx processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			      MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			      MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			      MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	config1 = read_c0_config1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (!(config1 & MIPS_CONF_M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	config2 = read_c0_config2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (!mips_sc_is_activated(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tmp = (config2 >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (tmp <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		c->scache.sets = 64 << tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	tmp = (config2 >> 0) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (tmp <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		c->scache.ways = tmp + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (current_cpu_type() == CPU_XBURST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		switch (mips_machtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		 * According to config2 it would be 5-ways, but that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * contradicted by all documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		case MACH_INGENIC_JZ4770:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		case MACH_INGENIC_JZ4775:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			c->scache.ways = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		 * According to config2 it would be 5-ways and 512-sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		 * but that is contradicted by all documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		case MACH_INGENIC_X1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		case MACH_INGENIC_X1000E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			c->scache.sets = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			c->scache.ways = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	c->scache.waysize = c->scache.sets * c->scache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	c->scache.waybit = __ffs(c->scache.waysize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int mips_sc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int found = mips_sc_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		mips_sc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		mips_sc_prefetch_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		bcops = &mips_sc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }