Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * r2300.c: R2000 and R3000 specific mmu/cache code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * with a lot of changes to make this thing work for R3000s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Tx39XX R4k style caches added. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/isadep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* For R3000 cores with R4000 style caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static unsigned long icache_size, dcache_size;		/* Size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* This sequence is required to ensure icache is disabled immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TX39_STOP_STREAMING() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	".set	 push\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	".set	 noreorder\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	"b	 1f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	"nop\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"1:\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	".set pop" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* TX39H-style cache flush routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static void tx39h_flush_icache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned long flags, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* disable icache (set ICE#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	write_c0_conf(config & ~TX39_CONF_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	TX39_STOP_STREAMING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	blast_icache16();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* Catch bad driver code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	BUG_ON(size == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	blast_inv_dcache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* TX39H2,TX39H3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline void tx39_blast_dcache_page(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (current_cpu_type() != CPU_TX3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		blast_dcache16_page(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	blast_dcache16_page_indexed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline void tx39_blast_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	blast_dcache16();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static inline void tx39_blast_icache_page(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long flags, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* disable icache (set ICE#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	write_c0_conf(config & ~TX39_CONF_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	TX39_STOP_STREAMING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	blast_icache16_page(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static inline void tx39_blast_icache_page_indexed(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long flags, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* disable icache (set ICE#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	write_c0_conf(config & ~TX39_CONF_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	TX39_STOP_STREAMING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	blast_icache16_page_indexed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void tx39_blast_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned long flags, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* disable icache (set ICE#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	write_c0_conf(config & ~TX39_CONF_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	TX39_STOP_STREAMING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	blast_icache16();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void tx39__flush_cache_vmap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void tx39__flush_cache_vunmap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline void tx39_flush_cache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (!cpu_has_dc_aliases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void tx39___flush_cache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	tx39_blast_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void tx39_flush_cache_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!cpu_has_dc_aliases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (cpu_context(smp_processor_id(), mm) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void tx39_flush_cache_range(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!cpu_has_dc_aliases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int exec = vma->vm_flags & VM_EXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct mm_struct *mm = vma->vm_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pmd_t *pmdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pte_t *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * If ownes no valid ASID yet, cannot possibly have gotten
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * this page into the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (cpu_context(smp_processor_id(), mm) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	page &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	pmdp = pmd_off(mm, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ptep = pte_offset_kernel(pmdp, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * If the page isn't marked valid, the page cannot possibly be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * in the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!(pte_val(*ptep) & _PAGE_PRESENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * Doing flushes for another ASID than the current one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * too difficult since stupid R4k caches do a TLB translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * for every cache flush operation.  So we do indexed flushes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * in that case, which doesn't overly flush the cache too much.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (cpu_has_dc_aliases || exec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			tx39_blast_dcache_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (exec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			tx39_blast_icache_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * Do indexed flush, too much work to get the (possible) TLB refills
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * to work correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (cpu_has_dc_aliases || exec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		tx39_blast_dcache_page_indexed(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (exec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		tx39_blast_icache_page_indexed(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void local_tx39_flush_data_cache_page(void * addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tx39_blast_dcache_page((unsigned long)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void tx39_flush_data_cache_page(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	tx39_blast_dcache_page(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void tx39_flush_icache_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (end - start > dcache_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		protected_blast_dcache_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (end - start > icache_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		tx39_blast_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		unsigned long flags, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/* disable icache (set ICE#) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		write_c0_conf(config & ~TX39_CONF_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		TX39_STOP_STREAMING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		protected_blast_icache_range(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		end = addr + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			tx39_blast_dcache_page(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		} while(addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} else if (size > dcache_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		blast_dcache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		end = addr + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			tx39_blast_dcache_page(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			addr += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		} while(addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	} else if (size > dcache_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		tx39_blast_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		blast_inv_dcache_range(addr, addr + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static __init void tx39_probe_cache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				  TX39_CONF_ICS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				  TX39_CONF_DCS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	current_cpu_data.icache.linesz = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case CPU_TX3912:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		current_cpu_data.icache.ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		current_cpu_data.dcache.ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		current_cpu_data.dcache.linesz = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case CPU_TX3927:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		current_cpu_data.icache.ways = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		current_cpu_data.dcache.ways = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		current_cpu_data.dcache.linesz = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case CPU_TX3922:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		current_cpu_data.icache.ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		current_cpu_data.dcache.ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		current_cpu_data.dcache.linesz = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void tx39_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	extern void build_clear_page(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	extern void build_copy_page(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	config = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	config &= ~TX39_CONF_WBON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	write_c0_conf(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	tx39_probe_cache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	case CPU_TX3912:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		/* TX39/H core (writethru direct-map cache) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		__flush_cache_vmap	= tx39__flush_cache_vmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		__flush_cache_vunmap	= tx39__flush_cache_vunmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		flush_cache_all = tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		__flush_cache_all	= tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		flush_cache_mm		= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		flush_cache_range	= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		flush_cache_page	= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		flush_icache_range	= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		local_flush_icache_range = (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		flush_data_cache_page	= (void *) tx39h_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		_dma_cache_wback_inv	= tx39h_dma_cache_wback_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		shm_align_mask		= PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	case CPU_TX3922:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	case CPU_TX3927:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		/* board-dependent init code may set WBON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		__flush_cache_vmap	= tx39__flush_cache_vmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		__flush_cache_vunmap	= tx39__flush_cache_vunmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		flush_cache_all = tx39_flush_cache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		__flush_cache_all = tx39___flush_cache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		flush_cache_mm = tx39_flush_cache_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		flush_cache_range = tx39_flush_cache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		flush_cache_page = tx39_flush_cache_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		flush_icache_range = tx39_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		local_flush_icache_range = tx39_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		flush_data_cache_page = tx39_flush_data_cache_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		_dma_cache_wback = tx39_dma_cache_wback_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		_dma_cache_inv = tx39_dma_cache_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		shm_align_mask = max_t(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 				       (dcache_size / current_cpu_data.dcache.ways) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 				       PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	__flush_icache_user_range = flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	__local_flush_icache_user_range = local_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	current_cpu_data.icache.sets =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	current_cpu_data.dcache.sets =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	current_cpu_data.icache.waybit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	current_cpu_data.dcache.waybit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		icache_size >> 10, current_cpu_data.icache.linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	pr_info("Primary data cache %ldkB, linesize %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		dcache_size >> 10, current_cpu_data.dcache.linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	build_clear_page();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	build_copy_page();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	tx39h_flush_icache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }