Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005-2007 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/bcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/war.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) unsigned long long cache_err_dcache[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) EXPORT_SYMBOL_GPL(cache_err_dcache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * Octeon automatically flushes the dcache on tlb changes, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * from Linux's viewpoint it acts much like a physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * tagged cache. No flushing is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static void octeon_flush_data_cache_page(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)     /* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline void octeon_local_flush_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	asm volatile ("synci 0($0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Flush local I-cache for the specified range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void local_octeon_flush_icache_range(unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					    unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	octeon_local_flush_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Flush caches as necessary for all cores affected by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * vma. If no vma is supplied, all cores are flushed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * @vma:    VMA to flush or NULL to flush all icaches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	extern void octeon_send_ipi_single(int cpu, unsigned int action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	cpumask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	octeon_local_flush_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * If we have a vma structure, we only need to worry about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * cores it has been used on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		mask = *mm_cpumask(vma->vm_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		mask = *cpu_online_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	cpumask_clear_cpu(cpu, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	for_each_cpu(cpu, &mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * Called to flush the icache on all cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void octeon_flush_icache_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	octeon_flush_icache_all_cores(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * Called to flush all memory associated with a memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * @mm:	    Memory context to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void octeon_flush_cache_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * According to the R4K version of this file, CPUs without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * dcache aliases don't need to do anything here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Flush a range of kernel addresses out of the icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void octeon_flush_icache_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	octeon_flush_icache_all_cores(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * Flush a range out of a vma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * @vma:    VMA to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * @end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void octeon_flush_cache_range(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				     unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (vma->vm_flags & VM_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		octeon_flush_icache_all_cores(vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * Flush a specific page of a vma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * @vma:    VMA to flush page for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * @page:   Page to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * @pfn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void octeon_flush_cache_page(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				    unsigned long page, unsigned long pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (vma->vm_flags & VM_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		octeon_flush_icache_all_cores(vma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * Probe Octeon's caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void probe_octeon(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned long icache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned long dcache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned int config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct cpuinfo_mips *c = &current_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int cputype = current_cpu_type();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	config1 = read_c0_config1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	switch (cputype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case CPU_CAVIUM_OCTEON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case CPU_CAVIUM_OCTEON_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		c->icache.linesz = 2 << ((config1 >> 19) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		c->icache.sets = 64 << ((config1 >> 22) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		c->icache.ways = 1 + ((config1 >> 16) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		c->icache.flags |= MIPS_CACHE_VTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		icache_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			c->icache.sets * c->icache.ways * c->icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		c->dcache.linesz = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (cputype == CPU_CAVIUM_OCTEON_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			c->dcache.sets = 1; /* CN3XXX has one Dcache set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		c->dcache.ways = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dcache_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			c->dcache.sets * c->dcache.ways * c->dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		c->options |= MIPS_CPU_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case CPU_CAVIUM_OCTEON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		c->icache.linesz = 2 << ((config1 >> 19) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		c->icache.sets = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		c->icache.ways = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		c->icache.flags |= MIPS_CACHE_VTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		c->dcache.linesz = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		c->dcache.ways = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		c->dcache.sets = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		c->options |= MIPS_CPU_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case CPU_CAVIUM_OCTEON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		c->icache.linesz = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		c->icache.sets = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		c->icache.ways = 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		c->icache.flags |= MIPS_CACHE_VTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		c->dcache.linesz = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		c->dcache.ways = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		c->dcache.sets = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		c->options |= MIPS_CPU_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		panic("Unsupported Cavium Networks CPU type");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* compute a couple of other cache variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	c->icache.waysize = icache_size / c->icache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	c->dcache.waysize = dcache_size / c->dcache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (smp_processor_id() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		pr_info("Primary instruction cache %ldkB, %s, %d way, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			"%d sets, linesize %d bytes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			icache_size >> 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			cpu_has_vtag_icache ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				"virtually tagged" : "physically tagged",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			c->icache.ways, c->icache.sets, c->icache.linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		pr_info("Primary data cache %ldkB, %d-way, %d sets, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			"linesize %d bytes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			dcache_size >> 10, c->dcache.ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			c->dcache.sets, c->dcache.linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void  octeon_cache_error_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	extern char except_vec2_octeon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	set_handler(0x100, &except_vec2_octeon, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * Setup the Octeon cache flush routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void octeon_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	probe_octeon();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	shm_align_mask = PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	flush_cache_all			= octeon_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	__flush_cache_all		= octeon_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	flush_cache_mm			= octeon_flush_cache_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	flush_cache_page		= octeon_flush_cache_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	flush_cache_range		= octeon_flush_cache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	flush_icache_all		= octeon_flush_icache_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	flush_data_cache_page		= octeon_flush_data_cache_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	flush_icache_range		= octeon_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	local_flush_icache_range	= local_octeon_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	__flush_icache_user_range	= octeon_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	__local_flush_icache_user_range	= local_octeon_flush_icache_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	__flush_kernel_vmap_range	= octeon_flush_kernel_vmap_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	build_clear_page();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	build_copy_page();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	board_cache_error_setup = octeon_cache_error_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * Handle a cache error exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static RAW_NOTIFIER_HEAD(co_cache_error_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int register_co_cache_error_notifier(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return raw_notifier_chain_register(&co_cache_error_chain, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int unregister_co_cache_error_notifier(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void co_cache_error_call_notifiers(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if ((rv & ~NOTIFY_STOP_MASK) != NOTIFY_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		u64 dcache_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		unsigned long coreid = cvmx_get_core_num();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		u64 icache_err = read_octeon_c0_icacheerr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			dcache_err = cache_err_dcache[coreid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			cache_err_dcache[coreid] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			dcache_err = read_octeon_c0_dcacheerr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		pr_err("Core%lu: Cache error exception:\n", coreid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (icache_err & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			pr_err("CacheErr (Icache) == %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			       (unsigned long long)icache_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			write_octeon_c0_icacheerr(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (dcache_err & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			pr_err("CacheErr (Dcache) == %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			       (unsigned long long)dcache_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * Called when the the exception is recoverable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) asmlinkage void cache_parity_error_octeon_recoverable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	co_cache_error_call_notifiers(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)  * Called when the the exception is not recoverable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) asmlinkage void cache_parity_error_octeon_non_recoverable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	co_cache_error_call_notifiers(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	panic("Can't handle cache error: nested exception");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }