^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* IEEE754 floating point arithmetic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * single precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * MIPS floating point support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1994-2000 Algorithmics Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ieee754sp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) int ieee754sp_class(union ieee754sp x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) COMPXSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) EXPLODEXSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) return xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static inline int ieee754sp_isnan(union ieee754sp x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return ieee754_class_nan(ieee754sp_class(x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline int ieee754sp_issnan(union ieee754sp x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int qbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) assert(ieee754sp_isnan(x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) qbit = (SPMANT(x) & SP_MBIT(SP_FBITS - 1)) == SP_MBIT(SP_FBITS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return ieee754_csr.nan2008 ^ qbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Raise the Invalid Operation IEEE 754 exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * and convert the signaling NaN supplied to a quiet NaN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) assert(ieee754sp_issnan(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ieee754_setcx(IEEE754_INVALID_OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ieee754_csr.nan2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SPMANT(r) |= SP_MBIT(SP_FBITS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SPMANT(r) &= ~SP_MBIT(SP_FBITS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!ieee754sp_isnan(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SPMANT(r) |= SP_MBIT(SP_FBITS - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* inexact must round of 3 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (xm & (SP_MBIT(3) - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) switch (ieee754_csr.rm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case FPU_CSR_RZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case FPU_CSR_RN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) xm += 0x3 + ((xm >> 3) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* xm += (xm&0x8)?0x4:0x3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case FPU_CSR_RU: /* toward +Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!sn) /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) xm += 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case FPU_CSR_RD: /* toward -Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (sn) /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) xm += 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return xm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* generate a normal/denormal number with over,under handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * sn is sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * xe is an unbiased exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * xm is 3bit extended precision value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) assert(xm); /* we don't gen exact zeros (probably should) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) assert(xm & (SP_HIDDEN_BIT << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (xe < SP_EMIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* strip lower bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int es = SP_EMIN - xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ieee754_csr.nod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ieee754_setcx(IEEE754_UNDERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ieee754_setcx(IEEE754_INEXACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) switch(ieee754_csr.rm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case FPU_CSR_RN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case FPU_CSR_RZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ieee754sp_zero(sn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case FPU_CSR_RU: /* toward +Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (sn == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ieee754sp_min(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ieee754sp_zero(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case FPU_CSR_RD: /* toward -Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (sn == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ieee754sp_zero(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ieee754sp_min(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (xe == SP_EMIN - 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ieee754sp_get_rounding(sn, xm) >> (SP_FBITS + 1 + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Not tiny after rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ieee754_setcx(IEEE754_INEXACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) xm = ieee754sp_get_rounding(sn, xm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) xm >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Clear grs bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) xm &= ~(SP_MBIT(3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) xe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* sticky right shift es bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) xm = XSPSRS(xm, es);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) xe += es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) assert((xm & (SP_HIDDEN_BIT << 3)) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) assert(xe == SP_EMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (xm & (SP_MBIT(3) - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ieee754_setcx(IEEE754_INEXACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if ((xm & (SP_HIDDEN_BIT << 3)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ieee754_setcx(IEEE754_UNDERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* inexact must round of 3 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) xm = ieee754sp_get_rounding(sn, xm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* adjust exponent for rounding add overflowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (xm >> (SP_FBITS + 1 + 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* add causes mantissa overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) xm >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) xe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* strip grs bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) xm >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) assert(xe >= SP_EMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (xe > SP_EMAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ieee754_setcx(IEEE754_OVERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ieee754_setcx(IEEE754_INEXACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* -O can be table indexed by (rm,sn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (ieee754_csr.rm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case FPU_CSR_RN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ieee754sp_inf(sn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case FPU_CSR_RZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ieee754sp_max(sn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case FPU_CSR_RU: /* toward +Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (sn == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ieee754sp_inf(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ieee754sp_max(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case FPU_CSR_RD: /* toward -Infinity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (sn == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ieee754sp_max(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ieee754sp_inf(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* gen norm/denorm/zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if ((xm & SP_HIDDEN_BIT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* we underflow (tiny/zero) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) assert(xe == SP_EMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ieee754_csr.mx & IEEE754_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ieee754_setcx(IEEE754_UNDERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) assert(xm & SP_HIDDEN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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