^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chen Huacai, chenhc@lemote.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched/hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kexec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <loongson.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <loongson_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <workarounds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "smp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_PER_CPU(int, cpu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void *ipi_set0_regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void *ipi_clear0_regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void *ipi_status0_regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void *ipi_en0_regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void *ipi_mailbox_buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static uint32_t core0_c0count[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* read a 32bit value from ipi register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define loongson3_ipi_read32(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* read a 64bit value from ipi register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define loongson3_ipi_read64(addr) readq(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* write a 32bit value to ipi register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define loongson3_ipi_write32(action, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writel(action, addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __wbflush(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* write a 64bit value to ipi register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define loongson3_ipi_write64(action, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writeq(action, addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __wbflush(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 (*ipi_read_clear)(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void (*ipi_write_action)(int cpu, u32 action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static u32 csr_ipi_read_clear(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Load the ipi register to figure out what we're supposed to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) action = csr_readl(LOONGSON_CSR_IPI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Clear the ipi register to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) csr_writel(action, LOONGSON_CSR_IPI_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void csr_ipi_write_action(int cpu, u32 action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) while ((irq = ffs(action))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uint32_t val = CSR_IPI_SEND_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val |= (irq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val |= (cpu << CSR_IPI_SEND_CPU_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) csr_writel(val, LOONGSON_CSR_IPI_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) action &= ~BIT(irq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static u32 legacy_ipi_read_clear(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Load the ipi register to figure out what we're supposed to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Clear the ipi register to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void legacy_ipi_write_action(int cpu, u32 action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void csr_ipi_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ipi_read_clear = csr_ipi_read_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ipi_write_action = csr_ipi_write_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ipi_read_clear = legacy_ipi_read_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ipi_write_action = legacy_ipi_write_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void ipi_set0_regs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ipi_set0_regs[0] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ipi_set0_regs[1] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ipi_set0_regs[2] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ipi_set0_regs[3] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ipi_set0_regs[4] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ipi_set0_regs[5] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ipi_set0_regs[6] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ipi_set0_regs[7] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ipi_set0_regs[8] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ipi_set0_regs[9] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ipi_set0_regs[10] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ipi_set0_regs[11] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ipi_set0_regs[12] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ipi_set0_regs[13] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ipi_set0_regs[14] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ipi_set0_regs[15] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void ipi_clear0_regs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ipi_clear0_regs[0] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ipi_clear0_regs[1] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ipi_clear0_regs[2] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ipi_clear0_regs[3] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ipi_clear0_regs[4] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ipi_clear0_regs[5] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ipi_clear0_regs[6] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ipi_clear0_regs[7] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ipi_clear0_regs[8] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ipi_clear0_regs[9] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ipi_clear0_regs[10] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ipi_clear0_regs[11] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ipi_clear0_regs[12] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ipi_clear0_regs[13] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ipi_clear0_regs[14] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ipi_clear0_regs[15] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void ipi_status0_regs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ipi_status0_regs[0] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ipi_status0_regs[1] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ipi_status0_regs[2] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ipi_status0_regs[3] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ipi_status0_regs[4] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ipi_status0_regs[5] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ipi_status0_regs[6] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ipi_status0_regs[7] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ipi_status0_regs[8] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ipi_status0_regs[9] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ipi_status0_regs[10] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ipi_status0_regs[11] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ipi_status0_regs[12] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ipi_status0_regs[13] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ipi_status0_regs[14] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ipi_status0_regs[15] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void ipi_en0_regs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ipi_en0_regs[0] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ipi_en0_regs[1] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ipi_en0_regs[2] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ipi_en0_regs[3] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ipi_en0_regs[4] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ipi_en0_regs[5] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ipi_en0_regs[6] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ipi_en0_regs[7] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ipi_en0_regs[8] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ipi_en0_regs[9] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ipi_en0_regs[10] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ipi_en0_regs[11] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ipi_en0_regs[12] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ipi_en0_regs[13] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ipi_en0_regs[14] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ipi_en0_regs[15] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void ipi_mailbox_buf_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ipi_mailbox_buf[0] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ipi_mailbox_buf[1] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ipi_mailbox_buf[2] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ipi_mailbox_buf[3] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ipi_mailbox_buf[4] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ipi_mailbox_buf[5] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ipi_mailbox_buf[6] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ipi_mailbox_buf[7] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ipi_mailbox_buf[8] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ipi_mailbox_buf[9] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ipi_mailbox_buf[10] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ipi_mailbox_buf[11] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ipi_mailbox_buf[12] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ipi_mailbox_buf[13] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ipi_mailbox_buf[14] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ipi_mailbox_buf[15] = (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Simple enough, just poke the appropriate ipi register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void loongson3_send_ipi_single(int cpu, unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ipi_write_action(cpu_logical_map(cpu), (u32)action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for_each_cpu(i, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ipi_write_action(cpu_logical_map(i), (u32)action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int i, cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int action, c0count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) action = ipi_read_clear(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (action & SMP_RESCHEDULE_YOURSELF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) scheduler_ipi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (action & SMP_CALL_FUNCTION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) generic_smp_call_function_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (action & SMP_ASK_C0COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BUG_ON(cpu != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) c0count = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) c0count = c0count ? c0count : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 1; i < nr_cpu_ids; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) core0_c0count[i] = c0count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __wbflush(); /* Let others see the result ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MAX_LOOPS 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * SMP init and finish on secondary CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void loongson3_init_secondary(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint32_t initcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) STATUSF_IP3 | STATUSF_IP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Set interrupt mask, but don't enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) change_c0_status(ST0_IM, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (i = 0; i < num_possible_cpus(); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) per_cpu(cpu_state, cpu) = CPU_ONLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cpu_set_core(&cpu_data[cpu],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cpu_data[cpu].package =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) core0_c0count[cpu] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while (!core0_c0count[cpu]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (i > MAX_LOOPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) i = MAX_LOOPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (cpu_data[cpu].package)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) initcount = core0_c0count[cpu] + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else /* Local access is faster for loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) initcount = core0_c0count[cpu] + i/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) write_c0_count(initcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void loongson3_smp_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) loongson3_ipi_write64(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pr_info("CPU#%d finished, CP0_ST=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) smp_processor_id(), read_c0_status());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void __init loongson3_smp_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i = 0, num = 0; /* i: physical id, num: logical id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) init_cpu_possible(cpu_none_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* For unified kernel, NR_CPUS is the maximum possible value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * loongson_sysconf.nr_cpus is the really present value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) while (i < loongson_sysconf.nr_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Reserved physical CPU cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __cpu_number_map[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __cpu_number_map[i] = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __cpu_logical_map[num] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) set_cpu_possible(num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pr_info("Detected %i available CPU(s)\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) while (num < loongson_sysconf.nr_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __cpu_logical_map[num] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) csr_ipi_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ipi_set0_regs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ipi_clear0_regs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ipi_status0_regs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ipi_en0_regs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ipi_mailbox_buf_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cpu_set_core(&cpu_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cpu_logical_map(0) % loongson_sysconf.cores_per_package);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void __init loongson3_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pr_err("Failed to request IPI IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) init_cpu_present(cpu_possible_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Setup the PC, SP, and GP of a secondary processor and start it runing!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long startargs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_info("Booting CPU#%d...\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* startargs[] are initial PC, SP and GP for secondary CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) startargs[0] = (unsigned long)&smp_bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) startargs[1] = (unsigned long)__KSTK_TOS(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) startargs[2] = (unsigned long)task_thread_info(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) startargs[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cpu, startargs[0], startargs[1], startargs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) loongson3_ipi_write64(startargs[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) loongson3_ipi_write64(startargs[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) loongson3_ipi_write64(startargs[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) loongson3_ipi_write64(startargs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int loongson3_cpu_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (cpu == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) set_cpu_online(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) calculate_cpu_foreign_map();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) irq_cpu_offline();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) clear_c0_status(ST0_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void loongson3_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) while (per_cpu(cpu_state, cpu) != CPU_DEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * flush all L1 entries at first. Then, another core (usually Core 0) can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * safely disable the clock of the target core. loongson3_play_dead() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * called via CKSEG1 (uncached and unmmaped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void loongson3_type1_play_dead(int *state_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) register int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) register long cpuid, core, node, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) register void *addr, *base, *initfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) " li %[addr], 0x80000000 \n" /* KSEG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) " cache 0, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) " cache 0, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) " cache 0, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) " cache 1, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) " cache 1, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) " cache 1, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) " addiu %[sets], %[sets], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) " bnez %[sets], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) " addiu %[addr], %[addr], 0x20 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) " sw %[val], (%[state_addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) " sync \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) : [addr] "=&r" (addr), [val] "=&r" (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) : [state_addr] "r" (state_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) " .set mips64 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) " mfc0 %[cpuid], $15, 1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) " andi %[cpuid], 0x3ff \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) " dli %[base], 0x900000003ff01000 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) " andi %[core], %[cpuid], 0x3 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) " sll %[core], 8 \n" /* get core id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) " or %[base], %[base], %[core] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) " andi %[node], %[cpuid], 0xc \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) " dsll %[node], 42 \n" /* get node id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) " or %[base], %[base], %[node] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "1: li %[count], 0x100 \n" /* wait for init loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "2: bnez %[count], 2b \n" /* limit mailbox access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) " addiu %[count], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) " beqz %[initfunc], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) " ld $a1, 0x38(%[base]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) " jr %[initfunc] \n" /* jump to initial PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) : [core] "=&r" (core), [node] "=&r" (node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [base] "=&r" (base), [cpuid] "=&r" (cpuid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [count] "=&r" (count), [initfunc] "=&r" (initfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) : /* No Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) : "a1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void loongson3_type2_play_dead(int *state_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) register int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) register long cpuid, core, node, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) register void *addr, *base, *initfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) " li %[addr], 0x80000000 \n" /* KSEG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) " cache 0, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) " cache 0, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) " cache 0, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) " cache 1, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) " cache 1, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) " cache 1, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) " addiu %[sets], %[sets], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) " bnez %[sets], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) " addiu %[addr], %[addr], 0x20 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) " sw %[val], (%[state_addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) " sync \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) : [addr] "=&r" (addr), [val] "=&r" (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) : [state_addr] "r" (state_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) " .set mips64 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) " mfc0 %[cpuid], $15, 1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) " andi %[cpuid], 0x3ff \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) " dli %[base], 0x900000003ff01000 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) " andi %[core], %[cpuid], 0x3 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) " sll %[core], 8 \n" /* get core id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) " or %[base], %[base], %[core] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) " andi %[node], %[cpuid], 0xc \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) " dsll %[node], 42 \n" /* get node id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) " or %[base], %[base], %[node] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) " dsrl %[node], 30 \n" /* 15:14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) " or %[base], %[base], %[node] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "1: li %[count], 0x100 \n" /* wait for init loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "2: bnez %[count], 2b \n" /* limit mailbox access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) " addiu %[count], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) " beqz %[initfunc], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) " ld $a1, 0x38(%[base]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) " jr %[initfunc] \n" /* jump to initial PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) : [core] "=&r" (core), [node] "=&r" (node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [base] "=&r" (base), [cpuid] "=&r" (cpuid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [count] "=&r" (count), [initfunc] "=&r" (initfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) : /* No Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) : "a1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void loongson3_type3_play_dead(int *state_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) register int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) register long cpuid, core, node, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) register void *addr, *base, *initfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) " li %[addr], 0x80000000 \n" /* KSEG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) " cache 0, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) " cache 0, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) " cache 0, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) " cache 1, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) " cache 1, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) " cache 1, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) " addiu %[sets], %[sets], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) " bnez %[sets], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) " addiu %[addr], %[addr], 0x40 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) " li %[addr], 0x80000000 \n" /* KSEG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) " cache 2, 1(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) " cache 2, 2(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) " cache 2, 3(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) " cache 2, 4(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) " cache 2, 5(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) " cache 2, 6(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) " cache 2, 7(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) " cache 2, 8(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) " cache 2, 9(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) " cache 2, 10(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) " cache 2, 11(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) " cache 2, 12(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) " cache 2, 13(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) " cache 2, 14(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) " cache 2, 15(%[addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) " addiu %[vsets], %[vsets], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) " bnez %[vsets], 2b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) " addiu %[addr], %[addr], 0x40 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) " sw %[val], (%[state_addr]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) " sync \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) : [addr] "=&r" (addr), [val] "=&r" (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) : [state_addr] "r" (state_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) " .set push \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) " .set noreorder \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) " .set mips64 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) " mfc0 %[cpuid], $15, 1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) " andi %[cpuid], 0x3ff \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) " dli %[base], 0x900000003ff01000 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) " andi %[core], %[cpuid], 0x3 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) " sll %[core], 8 \n" /* get core id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) " or %[base], %[base], %[core] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) " andi %[node], %[cpuid], 0xc \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) " dsll %[node], 42 \n" /* get node id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) " or %[base], %[base], %[node] \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "1: li %[count], 0x100 \n" /* wait for init loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "2: bnez %[count], 2b \n" /* limit mailbox access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) " addiu %[count], -1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) " beqz %[initfunc], 1b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) " ld $a1, 0x38(%[base]) \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) " jr %[initfunc] \n" /* jump to initial PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) " nop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) " .set pop \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) : [core] "=&r" (core), [node] "=&r" (node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [base] "=&r" (base), [cpuid] "=&r" (cpuid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [count] "=&r" (count), [initfunc] "=&r" (initfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) : /* No Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) : "a1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) void play_dead(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int prid_imp, prid_rev, *state_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void (*play_dead_at_ckseg1)(int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) idle_task_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) prid_imp = read_c0_prid() & PRID_IMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) prid_rev = read_c0_prid() & PRID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (prid_imp == PRID_IMP_LOONGSON_64G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) play_dead_at_ckseg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) switch (prid_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case PRID_REV_LOONGSON3A_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) play_dead_at_ckseg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case PRID_REV_LOONGSON3B_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case PRID_REV_LOONGSON3B_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) play_dead_at_ckseg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case PRID_REV_LOONGSON3A_R2_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case PRID_REV_LOONGSON3A_R2_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case PRID_REV_LOONGSON3A_R3_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case PRID_REV_LOONGSON3A_R3_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) play_dead_at_ckseg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) state_addr = &per_cpu(cpu_state, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) play_dead_at_ckseg1(state_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int loongson3_disable_clock(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) uint64_t core_id = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint64_t package_id = cpu_data[cpu].package;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int loongson3_enable_clock(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) uint64_t core_id = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) uint64_t package_id = cpu_data[cpu].package;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int register_loongson3_notifier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "mips/loongson:prepare",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) loongson3_enable_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) loongson3_disable_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) early_initcall(register_loongson3_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) const struct plat_smp_ops loongson3_smp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .send_ipi_single = loongson3_send_ipi_single,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .send_ipi_mask = loongson3_send_ipi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .init_secondary = loongson3_init_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .smp_finish = loongson3_smp_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .boot_secondary = loongson3_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .smp_setup = loongson3_smp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .prepare_cpus = loongson3_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .cpu_disable = loongson3_cpu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .cpu_die = loongson3_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #ifdef CONFIG_KEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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