^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <loongson1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_CEVT_CSRC_LS1X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if defined(CONFIG_TIMER_USE_PWM1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LS1X_TIMER_BASE LS1X_PWM1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LS1X_TIMER_IRQ LS1X_PWM1_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #elif defined(CONFIG_TIMER_USE_PWM2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LS1X_TIMER_BASE LS1X_PWM2_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LS1X_TIMER_IRQ LS1X_PWM2_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #elif defined(CONFIG_TIMER_USE_PWM3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LS1X_TIMER_BASE LS1X_PWM3_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LS1X_TIMER_IRQ LS1X_PWM3_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LS1X_TIMER_BASE LS1X_PWM0_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LS1X_TIMER_IRQ LS1X_PWM0_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void __iomem *timer_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static uint32_t ls1x_jiffies_per_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void ls1x_pwmtimer_set_period(uint32_t period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __raw_writel(period, timer_reg_base + PWM_HRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __raw_writel(period, timer_reg_base + PWM_LRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline void ls1x_pwmtimer_restart(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __raw_writel(0x0, timer_reg_base + PWM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __init ls1x_pwmtimer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) timer_reg_base = ioremap(LS1X_TIMER_BASE, SZ_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!timer_reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) panic("Failed to remap timer registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ls1x_pwmtimer_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static u64 ls1x_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int old_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 old_jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) raw_spin_lock_irqsave(&ls1x_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Although our caller may have the read side of xtime_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * this is now a seqlock, and we are cheating in this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * by having side effects on state that we cannot undo if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * there is a collision on the seqlock and our caller has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * retry. (Namely, old_jifs and old_count.) So we must treat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * jiffies as volatile despite the lock. We read jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * before latching the timer count to guarantee that although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * the jiffies value might be older than the count (that is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * the counter may underflow between the last point where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * jiffies was incremented and the point where we latch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * count), it cannot be newer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) jifs = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* read the count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) count = __raw_readl(timer_reg_base + PWM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * It's possible for count to appear to go the wrong way for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * reason:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * The timer counter underflows, but we haven't handled the resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * interrupt and incremented jiffies yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Previous attempts to handle these cases intelligently were buggy, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * we just do the simple thing now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (count < old_count && jifs == old_jifs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) count = old_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) old_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) old_jifs = jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return (u64) (jifs * ls1x_jiffies_per_tick) + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct clocksource ls1x_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "ls1x-pwmtimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .read = ls1x_clocksource_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .mask = CLOCKSOURCE_MASK(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static irqreturn_t ls1x_clockevent_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clock_event_device *cd = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ls1x_pwmtimer_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) raw_spin_lock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ls1x_pwmtimer_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) raw_spin_unlock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_lock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) raw_spin_unlock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) raw_spin_lock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) timer_reg_base + PWM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) raw_spin_unlock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int ls1x_clockevent_set_next(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) raw_spin_lock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ls1x_pwmtimer_set_period(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ls1x_pwmtimer_restart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) raw_spin_unlock(&ls1x_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct clock_event_device ls1x_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "ls1x-pwmtimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .features = CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .irq = LS1X_TIMER_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .set_next_event = ls1x_clockevent_set_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_state_shutdown = ls1x_clockevent_set_state_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .set_state_periodic = ls1x_clockevent_set_state_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .set_state_oneshot = ls1x_clockevent_set_state_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .tick_resume = ls1x_clockevent_tick_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void __init ls1x_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clock_event_device *cd = &ls1x_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!mips_hpt_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) panic("Invalid timer clock rate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ls1x_pwmtimer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clockevent_set_clock(cd, mips_hpt_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cd->max_delta_ns = clockevent_delta2ns(0xffffff, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cd->max_delta_ticks = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cd->min_delta_ns = clockevent_delta2ns(0x000300, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cd->min_delta_ticks = 0x000300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cd->cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ls1x_clocksource.rating = 200 + mips_hpt_frequency / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = clocksource_register_hz(&ls1x_clocksource, mips_hpt_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) panic(KERN_ERR "Failed to register clocksource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &ls1x_clockevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_err("Failed to register ls1x-pwmtimer interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* CONFIG_CEVT_CSRC_LS1X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk *clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* initialize LS1X clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ls1x_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_CEVT_CSRC_LS1X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* setup LS1X PWM timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk = clk_get(NULL, "ls1x-pwmtimer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) panic("unable to get timer clock, err=%ld", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mips_hpt_frequency = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ls1x_time_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* setup mips r4k timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clk = clk_get(NULL, "cpu_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mips_hpt_frequency = clk_get_rate(clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif /* CONFIG_CEVT_CSRC_LS1X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags